Design Engineer

Name : BIJJA GOPIKRISHNA

Email id :

******************@*****.***

Phone No : 898-***-****

Linkedin : https://www.linkedin.com/in/gopikrishna-bijja-53932b139

OBJECTIVE

To start my engineer career by joining a well settled and highly professional organization and grab good career advancement through large effort and innovative work techniques. EDUCATION

Institute of Aeronautical Engineering, JNTU-Hyderabad. Hyderabad, India Bachelor of Technology in Electronics and Communication Engineering, 65% May 2019 Narayana Junior college -- MPC 93% (2015) Hyderabad, India

SR digi school – SSC 88% (2013) Nizamabad, India

TECHNICAL SKILLS

• Simulation Tools: Cadence ( Innovus, Genus, Tempus, Virtuoso, QRC, Assura ), Calibre, Xilinx ISE, Matlab.

• Programming Languages: Verilog, TCL, Python, C.

• Operating System: Windows, Linux.

Diligent professional with strong electronics background and experience in Logic Synthesis and Physical Design. Hands on experience with 90nm and 130nm designs in Cadence Environment. PROFESSIONAL TRAINING

Institute of Silicon Systems –ASIC Physical Design May 2019 – October2019 Course Outline: VLSI Fundamentals, CMOS Basics, Digital Design, Logic Synthesis, Floor Planning, Power Planning, Placement and Routing, Clock Tree Synthesis, Static Timing Analysis, Timing Optimization, Cross Talk Analysis, DRC, LVS, Standard Cell Layout. PROJECTS

Project 1

ISS Wrapper [Block Level Design]

Objective : Timing Driven Layout

Tools : Cadence Innovus,

Tempus Gate Count/Area : 296,296/

1,508,801.9 um2 Macros/Std.Cells : 12/

25,195

Frequency : 200MHz

Technology/Layers : TSMC 90nm/ 5 metal Layers

Role: Perform Sanity Checks, Design import, Floor Planning, Power Planning, Placement, Trial Route, Congestion Analysis, RC Extraction, Timing Analysis, Clock Tree Synthesis, Detail Routing, Geometry Checks, Connectivity Checks, Antenna Violation Fixes, ECO Flows, Static Timing Analysis

Project 2

PCI Data [Top Level Design]

Objective : Timing Driven Layout

Tools : Cadence Innovus

Gate Count/Area : 128,929/ 1,572,529.1

um2 Blocks/Cells/IO : 12/ 24,450/ 120

Frequency : 150MHz

Technology/Layers : TSMC 90nm/ 5 metal Layers

Role: Perform Sanity Checks, Design import, Floor Planning, Power Planning, Placement, Trial Route, Congestion Analysis, RC Extraction, Timing Analysis, Clock Tree Synthesis, Detail Routing Project 3[Logic

Synthesis]

Counter_32

Objective : Running ZWLM and AWLM and compare PPA

constraints Tools : Cadence Genus

Clocks : 2

Frequency : 200MHz

Technology : TSMC90nm

Role: Writing SDC, TCL scripts, Generating reports for Area, Timing and Power Project 4[Logic

Synthesis]

Counter_256

Objective : Running ZWLM and estimate Maximum Possible Frequency of operation for RVT only, HVT only and Multi-VT cells Tools : Cadence Genus

Clocks : 1

Frequency : 541 MHz (RVT), 274 MHz (HVT), 537 MHz

(Multi-VT) Technology : TSMC90nm

Role: Writing SDC, TCL scripts, Generating reports for Area, Timing and Power Project 5

Standard Cells Layout Design

Objective : Design layouts for INVERTER, BUFFER, NAND, NOR, AND, OR, XOR Tools : Cadence Virtuoso, Assura

Technology/Layers : TSMC130nm

Role: Designing layouts using single metal layer and Verifying DRC/LVS, Meeting Half DRC rules by abutting standard cells

Independent Project

Title: Automation of Designing the logic for Processors. Description: As we know that lot of time in the project is being consumed by design and verification departments.

So in trying to reduce that time loss.

I have got an algorithm to design that RTL logic by machine, so that designing happens fast and there is not much requirement of verification for it because its been written by machine. I have written code for automatic generation of RTL logic for Combinational and synchronous logic with a type of code which is going to write the code on its own as per requirement. Advantages:

1 Reduces time taking to build and verify the RTL logic. 2 Reduces Human requirement.

B. Tech Projects

Major Project

Title: Analysis of Parallel Executable NOR based Content Addressable Memory (CAM) cells. Description: The project presents the Analysis of NOR based content addressable memory (CAM) Cells. As reducing the delay is becoming a basic need in data transfer of the networking this is more efficient than the existing conventional designs. To improve the functionality of the output in multiple matched cases a priority encoder is used. The proposed 16x8 CAM array design incorporates the enhanced array structures, decoder and priority encoder for better and reduced values of delays. These CAM arrays are designed using Cadence virtuoso tool with gpdk180 technology. The proposed CAM array operates at faster than the existing CAM array. This method gave better power-delay product which is lesser than the existing method.

Minor Project

Title: Shift register using Schmitt Trigger based Ram. Description: In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better writes ability compared to the standard 6T cell. The proposed ST bit cell incorporates a built-in feedback mechanism, achieving process variation tolerance -- a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130nm technology show that the proposed Schmitt Trigger bit cell gives 58% higher read Static Noise Margin (SNM), 2X higher write trip-point and 120mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage. Achivements

• Was awarded merit badge in Robotic workshop organized by ARK Robokart in association with IIT Madras.

• Was awarded runner-up in engineering level technical quiz by ELECTA.

• Led a team of 4 members to design Arduino Bipad Robot. Strengths

• Flexible and Adaptable

• Work under Stress

• Open minded

Interests and Hobbies

• Cosmology

• Learning new things

• Listening to Music

• Playing Video Games

Personal profile

Name : Bijja Gopikrishna

DOB : 13th September 1997

Father : Bijja Govardhan

Address : Fno 104, Apex Apartment, AC Guards,

Hyderabad. Languages : English, Telugu, Hindi.

Declaration

I hereby declare that the details furnished above are true and correct to the best of my knowledge.

Bijja GopiKrishna

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