CURRICULUM VITAE

NARASIMHA MURTHY MARRIPATI Ph no.: +91-998*******

D.NO: 65-6-407/1, E-mail id: addhwd@r.postjobfree.com

Mulagada Housing Colony, Gajuwaka Depot,

Visakhapatnam - 530026

PROFESSIONAL EXPERIENCE:

ACADEMIC CONSULTANT

(TOPPR TECHNOLOGIES PVT. LTD) (5TH DEC 2019 – 30TH DEC 2019) MANAGER (REALTY INFRA GROUP) (MAY 2019 - SEPTEMBER 2019)

Handling the Total Branch and entire Administration.

Created and maintained a marketing strategy for independent agents, working with and acquiring new advertising accounts and publications.

Hired and trained all new sales agents in all aspects of the job.

Organized all office activities, transactions, customer service and marketing strategies.

Raised office productivity and revenue in generating sales.

Lead overhaul in company website and social media campaigns that increased the branch search engine.

SOCIAL TEACHER (MARVEL SCHOOL) (JUNE 2012 – APRIL 2019)

Met parents and school governors; maintain discipline in the classroom; methodically provide resources for lessons; simplify lesson plans in line with curriculum objectives and assist students to prepare for examinations.

Assessing and looking after 120+ students’ progress throughout the term and work closely with other staff to efficiently plan and coordinate work.

Providing informative presentations to students regarding different areas of studies and ensure that all students fully comprehend all aspects.

Adopted distinctive teaching methodologies, documented all lessons, organized healthy group discussions, and mentored troubled students.

Proven track record of improving the progress of struggling students and increasing class test scores.

Coming to my main strength i am a multi tasker, where I am working as a photographer and as well as a FREELANCE designer for the same school.

Completed my mini project in “HINDUSTAN SHIPYARD LIMITED, VISAKHAPATNAM”. CAREER OBJECTIVES:

To pursue a challenging career and be a part of progressive organization that gives a scope to enhance my knowledge and utilizing my skills towards the growth of the organization. EDUCATIONAL QUALIFICATION:

Institution University/Board Branch

Pydah college of Engg And

Tech, Visakhapatnam.

JNTUK Electronics &

Communications

Muralidhar Educational

Institution IIT Academy,

VSP

Board of Intermediate, AP M.P.C

Zinc Smelter Senior

Secondary School, VSP.

CBSE 10th

SKILL SETS:

SKILL SET DESCRIPTION

Computer Applications Ms-office, Hardware & Networking, All Operating Systems, Photoshop.

Soft Skills Communication Skills.

KEY SKILLS:

Confident, Quick learner, self-motivated, dedicated, eager to learn more, high energy levels.

Good communication skills both written and verbal.

Easily adaptable to any changes, Carries a positive attitude.

Ability to analyze and think innovatively for improvement in the production and quality of work.

ACHIEVEMENTS:

Organized THE SPORTS EVENTS (Cricket and Volleyball) in the National Technical Symposium, INVENTO-2K12

Organized THE LAN-GAMING EVENT in the National Technical Symposium, INVENTO-2K12

Worked as One of the CORE COMMITEE MEMBER for Internationally Recognized, IMATTER

Participated in many district Inter School Level Singing Competitions.

Won the STATE 2ND PLACE IN HAMMER THROWS in the AP Inter District Athletics.

Selected for NATIONAL LEVEL ATHLETICS in Hammer throw.

I have consistently won the FIRST PLACE in both HAMMER THROW & SHOTPUT in the VSP District Athletics from the year 2008-2012.

Worked as a Volunteer in Many of my COLLEGE Events. PROJECT WORKS:

Title: DESIGN OF LOW POWER CMOS CIRCUITS IN NANOSCALE TECHNOLOGY Description: In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in sub threshold leakage current and hence static power dissipation. Although leakage power was negligible at 0.18µ technology and above, in nano scale technology, such as 0.09µ and 0.065µ, leakage power is almost equal to dynamic power consumption. Efficient leakage control mechanisms are crucial for saving power.

LECTOR is a static power reduction technique which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors (a p-type and a n-type) within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this arrangement, one of the LCTs is always “near its cutoff voltage” for any input combination. This increases the resistance of the path from Vdd to ground, leading to significant decrease in leakage currents. Further this technique overcomes the limitations posed by other existing methods for leakage reduction.

HOBBIES:

Photography

Playing Volleyball and Cricket.

Designing in Photoshop and CorelDraw.

Travelling

Gaining knowledge on World Wide Web

PERSONAL DETAILS:

Father’s Name : M.Tulasi Das

Nationality : Indian

Date of Birth : 7th November 1990

Languages known : English, Hindi, Telugu.

DECLARATION:

I do hereby declare that the above information is true to the best of my knowledge. Place: Visakhapatnam (M N MURTHY)

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