RANJEET PANCHOLY

*** ** ****** ****, ***** Park, CA 94025

addeof@r.postjobfree.com, +1-408-***-****

Semiconductors, Foundry, Technology, Manufacturing, Quality Engineering

Professional Experience

Kesar Technology, Menlo Park, CA 2013 to Present

Advance Technology Consultant and Founder and CEO, Renewable Energy Startup: Kesar Technology provides Consulting Services worldwide for Advance Semiconductor Technology Research and Development, Manufacturing Cost and Quality. Kesar Technology also produces Renewable Power Generation systems using innovative advance technology in Energy space.

Qualcomm Technologies, San Diego, CA 2010 – 2013

Director, Strategic Technology and Product Costing, Procurement Operations: At Qualcomm, I was responsible for Silicon Manufacturing Cost Optimization activities with Semiconductor Foundries and Package / Assembly subcontractors, which included Technology and Cost Assessments for Cost effective Technology insertion for Mobile Chip Sets. The key role was to align Cost optimization with Product Roadmaps, advanced Technology Availability, Maturity and Capacity planning with Foundry and Package Suppliers.

In this role, I developed manufacturing “Should Cost” models, defined Cost Reduction approaches and projected Competitive Product Cost for advanced Supplier Technologies, such as 28, 20 and 14 nm Bulk/ FINFET technologies, 130/110 Advanced PMIC technologies, 45 / 40 nm RF/SOI technologies, advanced POP Packages and for 3D Integration approaches for applications like Snapdragon Microprocessors, Mobile Power Management Devices, and RF devices. This activity with detailed process flow based cost models, resulted in introduction and cost optimization of over 30 ASIC circuits from strategic Silicon Foundries and Package and Assembly suppliers like TSMC, Global Foundries, Samsung, ASE and Amkor. The cost models were also used for Product Life time cost structure definition, ROI analysis and Competitive Product Analysis.

Seagate Technology, Scotts Valley, CA 1997 – 2009

Executive Director and Technologist - VLSI Manufacturing Technology and Supplier Quality Engineering: As Principal VLSI Manufacturing Technologist and Supplier Quality Engineer “Go To” person for Seagate Technology, I managed VLSI Electronic component Supply chain and Supplier Quality operations with a Team of 15 Engineers and Technologists. In this role, I interfaced with all ASIC Suppliers, Foundries and Package Suppliers, and defined Technology Roadmap aligned cost effective manufacturing strategies with Schedule, Capacity and Second Fab Sourcing considerations, Participated in Cost Negotiations and Cost Reduction Strategies, Monitored introduction of new ASICs from Tape Out to full Production, Resolved Technical Design, Process and Package Quality and Reliability issues, and Provided Life time support to all existing and new ASIC products.

In this role, I worked with internal worldwide cross functional teams of R and D, Engineering, Quality, Manufacturing Operations, and Supply Chain and interfaced with Suppliers like TSMC, Chartered Semiconductors (Now Global Semi), Texas Instruments, STM Microelectronics, LSI Logic, Marvell Semiconductors, Hynix, Micron, ASE and Amkor, etc. I also interfaced with worldwide Customers like EMC, Dell and HP for resolution of any Reliability and Quality issues.

During this time, over 65 new ASICs including Disk Drive Controllers with embedded Microprocessors and SRAMs, BCD and LBC Technology based Power Management Devices, Analog Mixed Signal BiCMOS Pre-Amplifiers, MEMs Accelerometers and Sensors, and Memories etc., were successfully ramped to production with low DPPM (<10 dppm) and fast TTM (Time to Market) and TTY (Time to Yield) (each < 6 months) from introduction.

My key achievement at Seagate was to define, improve and implement, a world class Technology development, ASIC Product Ramp and Manufacturing Quality Monitoring System, with statistical 6 Sigma Processes and Continuous Improvement approaches. This system significantly reduced supply chain disruptions and improved ASIC Product defect densities from >4000 DPPM to less than 10 DPPM resulting in a reduced Cost structure for the Disk drive manufacturing operation. This system has since been adopted in other Manufacturing plants of Seagate. I also qualified / requalified ISO 9000 standing of the company as well as audited Supplier for quality compliance.

To support this operation, I hired, mentored, developed and managed a worldwide team of 15 Senior Technologists, and experienced Supplier Quality Engineers to provide life time support all electrical components for 150M storage drives / Quarter manufacturing operation of Seagate Technology.

Quality Semiconductors, Cypress Semiconductors, AMI, etc. San Jose, CA 1984 -1997

Foundry Engineering, Semiconductor Advanced Technology Research and Development, and Technology Transfer: At Quality Semiconductors, I managed all ASIC Silicon Sourcing and Quality operations for cost effective manufacturing and Yield enhancement with spend budget of $20M / year. I worked with Suppliers such as TSMC, Chartered Semiconductor (now Global Semi), UMC, Toshiba, Seiko-Epson, TI and Package / Assembly suppliers like ASE and Amkor for new Technology planning, new ASIC design introductions and manufacturing of the ASIC products. I was responsible for end to end silicon supply chain operations including: Roadmap planning, Cost Negotiations, New Product Ramp to Manufacturing, Reliability Qualification and Product life time support.

Earlier at AMI, IMP and Cypress Semiconductor, as R&D Principal Investigator, I Developed, Qualified and Transferred to Manufacturing, a number of Technologies including several generations of CMOS VLSI, High Voltage BCD and LBC type technologies, and Analog BiCMOS technologies for internal Fab operations as well as for Foundry Services. I transferred over 10 technologies to Fabs in USA, China, Japan, Australia, Austria, India and South Africa.

Professional Activities

Over 30 Publications in International Research Journals and 5 USA Patents.

Conference Chairman and Technical Committee Member for VLSI Symposiums, Semi Industry Strategy Symposium (ISS) 2013-2014, IEEE Nano technology Council 2013-17, International Reliability Physics Symposiums, IEEE SOI/SOS Conferences, EOS/ESD Symposiums, and IEEE Nuclear Science Conferences.

Guest Editor, IEEE Transactions on Electron Devices and Solid State Technology.

United Nations UNDP Advisor to Semiconductor Complex, Government of India, for Technology Transfer and Silicon Manufacturing Facility development in India.

University of California, Los Angeles and University of California, Berkeley Extension Program Course Coordinator for several VLSI Technology and Circuits courses. Also Chairman, Santa Clara and Orange County Chapter of IEEE Electron Devices Society.

Education

Ph.D., Electrical Engineering, University of New Mexico, Albuquerque, NM. Research thesis on Fabrication and Radiation Effects on GaAsP/GaAs Schottkey FETs and LEDs.

M.S., Electrical Engineering, Oklahoma State University, Stillwater, OK.

M.Sc. and B.Sc., Physics, Birla Institute of Technology & Science, Pilani, India.

Management Training, Black Belt Six Sigma Certification, Seagate and Qualcomm Technologies.

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