Email: addduf@r.postjobfree.com

Phone: 602-***-****

OBJECTIVE:

Electrical Engineering position: Systems Engineer, System Test Engineer, Electrical/Electronics Engineer, FPGA Engineer, Reliability Engineer

TECHNICAL

SPECIALTIES:

Digital system and circuit design utilizing TTL, LVTTL, LVDS, CMOS, BICMOS, ECL logic families. Experience includes synchronous, asynchronous, state machine, analog interface (A/D, D/A, Comparators, Op-Amps), high-speed circuit design, digital PLL clock generation/clock distribution, CPU/memory/bus architecture, arithmetic, signal integrity experience, hardware/software integration and debug.

Proficient in top-down design methodology, which includes requirement analysis, decomposition, and implementation. Fluent in behavioral, structural, and rtl VHDL design, modeling, synthesis, test-bench development, and final silicon implementation using Mentor Exemplar and Leonardo Spectrum synthesis, Synplify Pro synthesis, and Mentor ModelSim products.

Devices: MACH, Cypress, Altera Stratix III/IV, Xilinx 3K/4K/5K/Virtex/Spartan, Lucent, Microsemi

Experience using microprocessor development /JTAG emulation systems. Experience using Python language.

LRU and board level hardware requirement specifications using requirement tracing tools (Siemens TcSE, IBM DOORS, IBM Rationale ClearCase (configuration management), ClearQuest (change management).

Production support and troubling-shooting avionic hardware and software. Experience working with other electronic hardware designers to coordinate, oversee, and review progress of the circuit designs.

Experience developing and presenting review-based material for project milestones.

System design, integration and test of electronic equipment interfacing to the following parallel and serial busses: TTGbE, 1553B Serial Bus Protocol, 1394B Fire Wire, ARINC 429 Serial Interface, IEEE 3488 control, PCI and Compact PCI, USB, 10/100/1000 Ethernet, RS-422(single driver), RS-485(multiple driver).

Power-supply design using VPT +28VDC DC-DC converters, integrated EMI filters and inrush current limiters. Additional power-supply design experience using highly efficient LDO regulators, power-supply monitors and multiple supply high-reliable architectures. Experience with ESD (human body model) and EMI (conductive and radiated) circuit design and test.

Mentor Graphics pcb DxDesigner, Xpedition, and Hyperlynx SI tools. Schematic generation, constraint driven layout for high-density multiple layer PCBs, pre layout and post layout signal analysis, cross-talk and impedance matching analysis, BGA and CGA package experience, buried via (multiple inner layers) and blind via (1-outer layer, 1 or more inner layers) architectures.

Education - BSEE - Fairleigh Dickinson University; DFSS – Honeywell 11/2002

EXPERIENCE

BASTION TECHNOLOGIES 09/2018 – 03/2019

Senior Reliability Engineer Analyst

Assigned to Jet Propulsion Laboratories space projects. These projects included Utopia Clipper verification and validation of flight systems and hardware reliability and mission environmental capability to ensure reliable operation in the harsh environment in space over the mission lifetime. I applied my hardware background to the EPSA – Electronic Parts Stress Analysis – which is a detailed evaluation of electronic components and margin requirements verification. In addition, experience identifying and tracking to closure problems, failure, or anomalies that involve or affect hardware. This experience was applied to the Mars 2020 rover project.

Have experience using MIL-HDBK-217F-Notice2 for reliability prediction of electronic equipment.

Experience creating worst-case circuit analysis (WCCA) which includes BOM evaluation.

In addition, I have FMECA (Failure Mode and Effects Analysis) experience which is a systematic analysis approach which facilitates the identification of potential problems in a design or process by examining the effects of lower level failure modes.

HONEYWELL AEROSPACE 01/2015 -01/2017

Senior Hardware Design Engineer – Flight Controls Hardware Engineering

Flash Memory component obsolescence replacement for production Servo hardware - including analysis and test verification

COMAC C919 Jet Flight Controls FPGA Hardware Verification/Validation procedure creation

Experience creating hardware procedures to verify multiple FPGA-based requirements

Exposure to Flight Control designs incorporating transformer isolation between lanes

Experience creating procedures for test script requirements

Experience using IBM Rationale ClearCase configuration management tool and ClearQuest change/tracking tool. Experience analyzing BOM and creating SCD’s for electrical and electronic components for final hardware designs.

ACSS 04/2012-10/2014

Sustaining Engineer

Component obsolescence circuit design modifications for Collision Avoidance System

Circuit worst-case analysis and signal integrity analysis to determine impact of new replacement components.

Replacement component selections resulted in SCD creation.

Circuits included analog, A/D, D/A, communication interfaces.

Circuit and LRU test fixture design using Corelis hardware/software JTAG ScanExpress products

Product test procedures modifications to accommodate design changes due to updated components

Experience using Freescale MPC8245 processors in multiple processor architecture - includes 133MHz SDRAM interface, WindRiver processor JTAG emulator

HONEYWELL AEROSPACE 05/2007 - 04/2012

System Engineer- Orion Network Integration Lab operations

Performed Orion Network ASIC integration and test in a risk reduction role

Developed following technical documents: milestone test plans, test procedures, test reports

Developed system test scripts in Python language to test and evaluate network ASIC’s

Experience with configuration and test of 1Gbit TTE targeted to Honeywell ASICs and Altera FPGA development fixtures including hardware Verification and Validation

System Engineer- Orion Vehicle C&DH VMC System Specification Development

Developed VMC box level hardware requirement specifications

LRU-level hardware requirements decomposed into circuit card-level requirement specifications

Worked with electronic hardware design teams to oversee and review the progress of the circuit card design, development, and test activities

Responsible for developing high-integrity network interface card (HNIC) requirements and designing/testing bread-board prototype circuit cards

Involved in circuit-card electronic packaging

HONEYWELL AEROSPACE 04/2002 - 04/2007

Product Engineer- Precision Components Operations

B-1B Air Data Computer:

Responsible for hardware obsolescence, reliability design changes identification, and customer site product test and analysis

Developed circuit designs, fault reports, and flight test report analysis. Design included flash-based FPGA design using rtl VHDL, embedded processor design/test/debug. Experience using 8051 custom Delta-Sigma 12-bit A/D ASIC

F-16 Air Data Computer:

Involved in digital hardware design incorporating re-use of original design processor technology

Experience with ARM7-TDMI based ASIC I/O interface, A/D interface, MIL-STD-1553 RT, silicon-based pressure sensor interface. Responsible for ARM7 SW A/D interface design/test and debug.

F-35 Air Data Computer:

Responsible for hardware design team management, customer review data requirements, schedule and task assignments

Design based on top-down hardware architecture based on customer requirements

Designed IEEE 1394B FireWire FPGA-based circuit card – included hardware/software interface, host processor architecture and external device interfaces

Architected/designed/tested/integrated 8051 based high-voltage controller for wing deicer. Controller contained embedded algorithms for closed loop algorithm and hardware interfaces to +270VDC deicer circuitry.

Managed hardware build, test and integration activities

Developed qualification requirement plan and procedures

AG COMMUNICATION SYSTEMS 06/1996-03/2002

Hardware Design Engineer

Developed circuit and packet switched telephony equipment

Developed TI-DSP32C based BER tester firmware design for ISDN interface

Designed Intel-80960 processor and ATM fabric-switch board and FPGA design. Responsible for test and application sw - processor architecture was high-reliability synchronization to achieve 99.999% reliability

Responsible for multiple-dsp based VOIP – voice / Ethernet / T1 processing board designs

Developed TI-DSP1620 based HDLC interface firmware design

Experience designing hot insert/removal interfaces, high-speed backplanes, high reliable micro-sync processor and clock distribution circuits. Experience using CPCI bus.

Designs responsibility included requirement analysis, architecture team involvement, schedule and task assignment, product integration and system test

Responsible for board placement and routing guidelines for CAD department using Mentor-based CAE tools, unit test board test fixture design, agency compliancy testing, corporate documentation support, and production support.

ACOUSTIC IMAGING 09/1990-05/1996

Hardware/DSP Design Engineer

Designed DSP software and digital hardware for ultrasound doppler processing system.

Experience designing hardware interfaces/software for the following DSPs: DSP16A, DSP1610, ADSP21020. Experience designing hw for the following 32-bit RISC processor: AM29205

Designed 32-bit RISC sw for AM29205 processor. This sw included Doppler application and DSP real-time interface for task and signal processing scheduling

Design experience using ECL clock generator/system timing circuit design, rtl VHDL targeted MACH, MAX, XILINX, and standard CPLD components, array multiplier signal processing algorithm design

Experience with JTAG scan hardware for test and embedded processor emulation

Experience as technical leader for hardware and software engineers of the doppler processing group

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