Paul D. Rocha

*** ******** *****

Cary, NC 919-***-****

OBJECTIVE: To secure an analog layout design position with a company in which my years of experience and abilities as a layout design engineer will be used to enhance the growth of the company.

TECHNICAL SKILLS: Cadence Virtuoso, Assura DRC/LVS/ERC, CMOS,

BiCMOS, Analog, Mixed Signal, Floorplanning, BiPolar,

Digital, Matching, Coupling, Latchup prevention, Interdigitation.

WORK EXPERIENCE:

Oct. 19-Present I.C. LAYOUT DESIGNER, NORTHROP GRUMMAN, BALTIMORE, MD

Custom layout of Reciprocal Quantum Logic, using Cadence

Virtuoso in proprietary process. Assura DRC/LVS.

May 19-Aug. 19 I.C. LAYOUT DESIGNER, CIRRUS LOGIC, AUSTIN, TX

Custom layout of cmos, mixed signal integrated circuits, using Cadence

Virtuoso in 22 NM TSMC. Also worked with 55 NM TSMC process.

Feb.18-Feb.19 I.C. LAYOUT DESIGNER, MICRON, MINNEAPOLIS, MN

Custom layout of cmos, mixed signal integrated circuits, using Cadence

Virtuoso in 28 NM TSMC. Also worked with 16 NM TSMC process.

Feb.16-Dec.17 I.C. LAYOUT DESIGNER, QORVO, GREENSBORO, NC

Custom layout of cmos, mixed signal integrated circuits. For example:

RF sections and controllers using CADENCE VIRTUOSO software and

CALIBRE verification software. Used UMC and IBM processes.

Apr.15-Dec.15 I.C. LAYOUT DESIGNER, INTEL, HILLSBORO, OR

Custom layout of cmos, mixed signal integrated circuits. For example:

RF amps and comparators using CADENCE VIRTUOSO software and

CALIBRE verification software. Used 28nm INTEL process.

Nov.14-Mar.15 I.C. LAYOUT DESIGNER, ASICNORTH, RALEIGH, NC

Custom layout of cmos, mixed signal integrated circuits. For example:

12 Bit SARADC and more using CADENCE VIRTUOSO software and

CALIBRE verification software. Used 14nm IBM process.

Aug.13-Oct.14 I.C. LAYOUT DESIGNER, QUALCOMM, RALEIGH, NC

Custom layout of cmos, bi-cmos, and bipolar, mixed signal, application

specific integrated circuits using CADENCE VIRTUOSO software and

CALIBRE verification software. Used 28, 20 and 16nm TSMC process.

Apr.13-Aug.13 I.C. LAYOUT DESIGNER, BROADCOM, IRVINE, CA

Custom layout of cmos, bi-cmos, and bipolar, mixed signal, application

specific integrated circuits using CADENCE VIRTUOSO software and

CALIBRE verification software. Used 28 Nanometer TSMC process.

Apr.04-Apr.13 I.C. LAYOUT DESIGNER, LINEAR TECHNOLOGY, CARY, NC

Custom layout of cmos, bi-cmos, and bipolar, mixed signal, application

specific integrated circuits using CADENCE VIRTUOSO software and

ASSURA verification software. Chips included 14 bit DACs, LED Drivers,

and Power Mgmt ICs.

Jan.97-Apr.04 ADJUNCT FACULTY, DALLAS COUNTY COMM. COLLEGE DISTRICT, TX

Instructed both Basic & Advanced Integrated Circuit Layout Design classes. Topics included, but not limited to: creation and layout of basic and complex logic, and Analog (Mixed Signal) layout techniques and concerns, such as matching, die area usage, power bussing, etc. Also co-authored two textbooks used in the course.

Dec.95-Feb. 04 I.C. LAYOUT DESIGNER, TEXAS INSTRUMENTS, DALLAS, TX

Custom layout of high-power, mixed signal, application specific integrated

Circuits using CADENCE VIRTUOSO software and site-specific verification

software package(SV/DV). Worked in Computer Peripherals and Wireless.

Jun.95-Dec. 95 I.C. LAYOUT DESIGNER, MOTOROLA SPS, Austin, TX

Responsible for planning and layout of custom BiCMOS periphery and core cells used in a fast, static RAM. Layout using Mentor Graphics IC Station.

Mar.95-June 95 I.C. LAYOUT DESIGNER, INTEL CORP., Santa Clara, CA

Custom contract layout and yield improvement edits made to cells in a high speed 686 based microprocessor. Used DLS design hybrid software of Cadence.

Oct.94 - Mar.95 I.C. LAYOUT DESIGNER, DIGITAL EQUIPMENT CORP., Austin, TX

Custom contract layout of high-speed digital microprocessor cells.

Responsible for yield improvement edits to data path and control portions of

high- speed microprocessor using MAESTRO Layout software

Apr.94 - Oct.94 I.C. LAYOUT DESIGNER, CYRIX CORP., Austin, TX

Custom contract layout of high-speed digital microprocessor cells. Solely responsible for layout of microsequencer and data path sections of Pentium compatible chip using Cadence OPUS 4.2.1 software.

Sep.93 - Apr.94 I.C. LAYOUT DESIGNER, IMP INC., Pleasanton, CA

Custom layout of VLSI circuits; digital, analog, and mixed-signal. Included layout of cells such as offset modulators, reference generators, and pad cells.

Feb. 88-Feb.92 U.S. Army, Airborne Infantry

Participated in Operations Desert Storm and Desert Shield.

EDUCATION: Institute for Business and Technology Jan. 93 - Sep. 93

CMOS Layout Design

CMOS processing/masking fundamentals and terminologies.

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