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Engineer Design

Prescott Valley, AZ, 86314
May 17, 2020

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Jerry R. Schumacher

**** *. ******** ***.

Prescott Valley, AZ 86314




Arizona State University

Tempe, Arizona

Degree: B.S. Electrical Engineering

Specialization: Microprocessor Systems Design

Graduation: May, 1980

Additional Education

ASU: One year of post-graduate work in embedded systems.

Phoenix College: C Programming, UNIX Programming.


Most of my experience has been in the area of microprocessor systems development, imbedded controller applications, and digital systems both in the hardware design and the firmware/software development.

I have thirty years designing systems using Motorola, Intel, Zilog, Fairchild, T.I., PIC, and ARM family of processors and have developed assembly language programs for all of them. I have developed programs in the higher level languages of Pascal, Basic, C and C++; and I have experience in programming in Fortran and Lisp.

I have six years experience in writing drivers, RTOS, and test functions for the embedded systems I have designed using C and C++. I have also written GUI’s using Visual C++ and Microsoft Foundation Class.

I have twenty years of experience designing complex high-speed combinatorial logic and complex state machines in FPGA's and PLD’s using the XILINX, ALTERA, and INTEL systems and I am a licensed XILINX developer. I have developed FPGA’s using schematic capture and VHDL and have simulated all of my designs using the Xilinx, Altera, or FPGA Express development systems. My designs included complex state machines, serial data converters, video synch circuits, etc.

I have designed analog amplifiers, Op-Amp circuits, feedback circuits, A/D and D/A interfaces, GPS, RS-232/245 interfaces, PCI bus interfaces, SPI Bus, I2C Bus interfaces, and MOSFET power and switching circuits.

I was responsible for doing the board layout on all of the systems that I have designed.

While designing military projects I have done thermal and failure analysis on my designs per MIL-SPEC.

I have held a management position supervising engineers, technicians and support people at Pathcor, Wavephore Inc, and Philips Semiconductor Inc. I have done labor and cost analysis, pert charts, etc., for the projects that I was directly involved in for fifteen years. I have designed using ViewLogic, Protel, Orcad, and Mentor Graphics and have developed library parts for all of them including setting up the Mentor libraries at Philips and the Orcad libraries at Pathcor.

Patents: “Configuration Graphical User Interface” applications program. Pat No US-030079.

Former Clearances: Secret, Top Secret, Crypto Top Secret.

Military Service: U.S. Navy; Electronic Tech PO2. Vietnam Veteran.

Hobbies: Golf, Playing the Guitar (60’s music), SCUBA, and Astronomy.

Affiliations: Mensa.


Feb 2004 – July 2009 Apogen Technologies

2414 West 12th St.

Tempe, AZ 85281

Position: Chief Engineer

Active Clearance: Secret

Responsibilities: To design specific systems using imbedded processors, CPLDs, Memory devices, and communication interfaces. The Xilinx CPLDs were developed using Xilinx 9.2I development system VHDL and simulated using ModelSim XE III. I designed an imbedded PIC processor sub-system and was instrumental in writing the firmware for the imbedded PIC processor using C++. I also wrote test drivers for the PIC processor in C++. I also designed another system using the Philips XA-S3 imbedded processor and the Xilinx Coolrunner II CPLDs using VHDL. Designed USB, Bluetooth, I2C, GPS, RS-232/245, and SPI interfaces for the embedded systems. Designed power circuits and electronic switches using a variety of MOSFET devices.

Did schematic design using Orcad 10.0i and developed all of the Orcad part libraries that are being used at Apogen.

Directed junior engineers and technicians.

2003 – Feb 2004 Mesa Public Schools

Position: Substitute Teacher

Responsibilities: Teaching High School math and science.

Oct 1999 – Oct 2002 Philips Semiconductor Inc

8375 South River Parkway

Tempe, Ariz 85234

Position: Senior Staff Engineer

Responsibilities: To direct junior engineers in the design and testing of proto-type and development boards used to exercise and develop ASICs designed by Philips. To do the system level design of development boards used with the ASICs. To direct a board project from conception through to the final testing. To design the interfaces between the Philips proprietary busses (PI, I2C, etc) and the PCI bus structure, both 33MHz and extended 66MHz 3.3V compact PCI Bus.

To do the system level design on the Nexperia rapid silicon development platform (NAPA) and direct the design of the NAPA system. This included designing high-speed FPGAs using Xilinx and Altera FPGAs and designing with MAX-PLUSII, FPGA Express, and Quartus development systems. Helping design the high-speed (400 MHz) NAPA bus.

To develop the RTOS for the embedded server in “C++” that interfaced with the GUI operating system.

To write embedded code for the ARM 946 development system using “C”.

To develop embedded control systems for testing functionality of large system-on-chip ASICs.

To develop hardware and drivers for testing the JTAG boundary scan on the SOCs. The drivers were developed using “C”.

I also helped put together the new Philips Mentor library.

To do the system level design on two separate Bluetooth products.

To develop a GUI using MFC in visual C++ for controlling the embedded server and doing the functional testing of the NAPA RSP system.

All hardware designs were documented using Mentor Graphics schematic and board development system.

May 98 – May 99 Motorola Satellite Communications Group

2501 S. Price Rd.

Chandler, Ariz.

Position: Principle Systems Engineer (Contract)

Responsibilities: To define the architecture for the interfaces between the Teledesic satellite host computers and the modem and tuners used in the uplink and downlink sections of the satellite payload. To develop the concept for a hardware table search engine function that would have been used to determine the hardware allocation of uplink resources in the Teledesic satellite system. This position was all theoretical analysis, there was no hardware or software design done.

Jan 96 - March 98 AG Communications

2500 W. Utopia Rd.

Phoenix, Ariz

Position: Sr. Design Engineer (Contract)

BRI Project:

Responsibilities: To design a portion of the Basic Rate Interchange system which will be part of the new ISDN phone switching system. Designed the Line Card interface using a Motorola 68340 Processor that also interfaced with a Motorola M68360 Processor. The system also required the use of some complex control logic and state machines which were implemented in a Xilinx 5200 series FPGA. The K2 data interface, which required reformatting of numerous data streams, was implemented in a Xilinx 4000E series FPGA. The K2 interface was quite complex and I had to use the Xilinx simulator, floor-planner, and X-Delay to decrease the amount of routing delays in the part to increase the efficiency.

CM4X Project:

Responsibilities: To design a portion of the controlling chip for the XMCT card that controls access to a 32-megaword common memory area using an Altera FLEX 10K100 FPGA. The FPGA design included parity checkers, information registers, combinatorial controlling logic, and a one-hot state machine. The design was developed using VHDL.

Also designed another 10K100 FPGA that was used as the interface controller to the systems main processor controller. This FPGA also had registers, combinatorial control logic, and four independent state machines and was also developed using VHDL.

Also designed a clock monitor chip using an Altera EPM7064 EPLD that checked four independent asynchronous clock inputs and generated controlling logic to determine which would be the primary system clock. It also generated clock alarms depending on any input faults.

May 94 - Dec 95 MetaLink Inc

325 E. Elliot Rd. Suite 23

Chandler, Ariz 85225

Position: Sr. Design Engineer

Responsibilities: To design Emulators for the OKI 65K and NEC K4 series of processors

using Altera and Xilinx FPLDs and the Intel 451 processor. I was also responsible for

writing the application drivers for the probe and interface cards in “C” and assembly language.

April 93 - May 94 IDEA Courier Inc.

1515 W. 14th St.

Tempe, Ariz 85282

Position: Sr. Design Engineer

Responsibilities: To design a 200 Mbs fiber-optic interface card between the IBM

ESCON technology and a high speed VL- Bus using an Intel i960 risc controller and a

series of Intel's iFX780 FPGAs. The development of the FPGAs was done using AHDL

and the simulation on ViewSim. To design a DRAM controller for the cards main memory and a bus arbitration system between the i960 and the VL-Bus. To write a driver program in “C” for downloading the iFX780 configuration programs.

Sept 91 - April 93 WavePhore Inc.

2601 W. Broadway Rd.

Tempe, Ariz 85282

Position: Digital Design Manager.

Responsibilities: To coordinate the design activities of three engineers and two

technicians in the development of a video data modem, including the technical

development of the design. To set design and cost schedules for development projects.

To design XILINX FPLD's that develop control signals based on incoming video. To

design the systems main controller using an 80C51 and develop the operating system

software. The development of the operating system was done using 8051 assembly language

and “C”. To write application specific software in “C” for manipulation of XILINX load files.

Sept 90 - Dec 90 Unidynamics Corp.

1000 N. Litchfield Rd.

Goodyear, Ariz. 85338

Position: Sr. Design. Engineer. (Contract)

Responsibilities: To redesign an Automatic Test System and integrate it with the

operating software. The operating system was written in Quick Basic.

June 1989 - Sept 1989 AG Communications Systems

2400 W. Utopia Rd.

Phoenix, Ariz.

Position: Sr. Design. Engineer. (Contract)

Responsibilities: To test and integrate the multi-processing sub-system that I had

designed for GTE the following year into the GTD-5 system. Job assignment included

writing real time test code in 80186 assembly code and “C” for evaluation of system

design and integration. To test functionality of the multi-processing system and check

system timing using a PC-based emulator and an HP logic analyzer.

Mar 1988 - Dec 1988 GTE Communications Systems

2400 W. Utopia Rd.

Phoenix, Ariz.

Position: Sr. Design. Engineer. (Contract)

Responsibilities: Design and development of a micro-synch processor system using two

Intel 80386 microprocessors for real time fault checking of the system. The OS was developed in 80386 assembly language. This system was to be used as the controller for a hard disk storage unit. Design and development of a multi-processing system using three Intel 80C186 microprocessors functioning as a high speed HDLC data link. I was responsible for the entire design of this system including utilization of the ALTERA high density MAX-PLD’s and Signetics high density PAL’s to reduce the chip count on the board. Other responsibilities included re-designing four cards in the GTE GTD-5 telephone switch system that are used to control the central memory unit and writing application test software in “C” to test the systems.

Aug 1987 - Oct 1987 Courier Terminal Systems

1515 W. 14th St.

Tempe, Ariz.

Position: Sr. Design. Engineer. (Contract)

Responsibilities: Design and development of a complex 40MHz high speed control state

machine using FAST MSI chips for controlling an IBM compatible video display.

Nov 1986 - Mar 1987 Unidynamics Corp.

1000 N. Litchfield Rd.

Goodyear, Ariz. 85338

Position: Sr. Design. Engineer. (Contract)

Responsibilities: Design and development of a Fairchild 9450 20MHz processor

system used to control the firing jets on a jet assisted ejection seat for a fighter aircraft.

This also included writing assembly language programs for self-testing of the control

system per MIL-SPEC 1750.

July 1983 - Sept 1986 Fairchild Data Corp.

350 N. Hayden Rd.

Scottsdale, Ariz. 85257

Position: Sr. Design Engineer

Responsibilities: Design and development of microprocessor based systems including both the hardware and firmware portions of the design for controlling complex communications systems. Design of digital decoders including Viterbi decoders, encoders, and digital signal processing equipment. Design of the digital sections of the Modulators and Demodulators including the control sections. Software development of the operating systems code using both assembly and Pascal code. Design of automatic test equipment for thorough functional testing of the microprocessor systems including writing drivers in assembly language. Analysis of labor and development time, cost analysis of development projects, supervision of Engineers and technicians working on the projects. Designs incorporated the Z-80 microprocessor as the controlling unit and the TI-32010 DSP to function as a digital decoder. Wrote the OS for the Z-80 processor and the drivers for the DSP in assembly language.

Jan. 1983 - May 1983 Space Data Corp.

1333 W. 21st Street

Tempe, Ariz. 85281

Position: Project Engineer

Responsibilities: Design and development of multi-processing systems using the Z-8002

and MC146805E2 Microprocessors, both the hardware and firmware portions of the

design including complete system integration and test. Firmware was developed on the

HP 64000 emulator. Design and implementation of a tape operating system to be used as

a memory backup system. Operating systems were developed using assembly language

of the corresponding processors.

Clearance: Secret

Feb 1980 - Oct 1982 Motorola Inc.

Government Electronics Group

Position: Sr. Design Engineer

Responsibilities: Design and development of combinatorial logic control systems, A/D

and D/A circuits, and digital interfacing between control systems and Host computers.

Design of alpha-numeric display systems. Design and implementation of automatic test

equipment for the systems designed. Design of an Intel 8086 microprocessor system for

controlling a large radar system. Design and development of the systems operating code

using Pascal, Basic and assembly language. All designs were done to MIL-SPEC levels.

Clearance: Top Secret.

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