OBJECTIVE

To obtain a position that allows me to utilize my knowledge and prior work experience in a team oriented environment.

JOB INTERESTS

Electronic Devices, Process engineering, R&D engineering, product development, technology enhancement, semiconductor testing, processing and testing Equipment.

CURRENT POSITION

Senior Electrical Engineer, Smiths Interconnect, Kansas City, KS, USA [Jan, 2018 – present].

EDUCATION

PhD: Electrical and Computer Engineering, New Jersey Institute of Technology, USA, 2007-2012.

Masters: Materials Science, Indian Institute of Technology, Kanpur, India, 2005-2007.

Undergraduate: Electronics and Communication Engineering, Institute of Engineering and Technology, Kanpur, India, 2000-2004.

PROFESSIONAL EXPERIENCE

-Senior Electrical Engineer, Smiths Interconnect [Jan, 2018 – present]

Technology development of spring probes, connectors, RF devices and semiconductor test sockets

Technology enhancement of company products

Writing white papers, filing patent of new technology, oral presentations in international conferences

Introduced new technologies such as inkjet/super inkjet printing, additive manufacturing (3D printing, micro molding, extrusion), silver/gold maxphase plating, packaging of bare silicon die etc. for company products

Collaborating design engineer, test engineer and product engineer

-Product Development Engineer, Anticipate Venture, USA [June, 2017 – Dec, 2017]

Designing and power testing of UV Lamp

Advancement and modification of lens system

-Process Integration, Micronova, Finland [Aug, 2016 – May, 2017]

Fabrication and characterization of Interdigitated Back Contact (IBC) solar cells using black silicon as front passivation

Micro PCD measurements to see edge effects on silicon wafer

Characterization of silicon wafer

-Asst. Professor, BITS Pilani and NCU INDIA [Jan, 2015 – July, 2016]

Teaching and research in Electrical Engineering

Mentoring undergraduate projects

Courses Taught: Semiconductor material and device characterization, VLSI technology and fabrication, Semiconductor device modeling and technology, Analog electronics.

-Process Integration, Center for Integrated Nanotechnologies, Sandia National Lab, Albuquerque, NM, USA [Dec, 2013 – Aug, 2014]

Back passivation of CdTe (compound semiconductor) using different oxides.

Defect study in p-CdTe etc.

-Process Integration, High Density Electronic Center, Fayetteville, Arkansas, USA [Jan, 2012 – Aug, 2013]

Fabrication of plasmonic structure using e-beam lithography for the enhancement of light trapping in amorphous silicon.

Characterization of amorphous silicon using Spectroscopic Ellipsometer.

-Project Assistant: National Renewable Energy Laboratory (NREL), Golden, Colorado, USA [July, 2008 – Dec, 2011]

Mesa diode arrays were fabricated and characterized to see the effect of dislocations which are non-uniformly distributed on polycrystalline silicon wafer.

Characterization of solar cells: I-V, C-V, Lock in Thermography, Light Beam Induced Current, Photoluminescence.

Matlab programming of dislocation model.

-Project Assistant: Samtel Center for Display Technology, I.I.T Kanpur, India [Jan, 2005 – Aug, 2007]

Fabrication and characterization of Organic thin film transistors (OTFT) using the composite dielectric of alumina and PMMA.

A majority of the devices were fabricated on a glass substrate, but flexible and rollable substrates made up of plastics were also used.

The fabrication process was done in a class 1000 cleanroom at Samtel Center, I.I.T Kanpur.

PATENTS

-Systems and methods for transient voltage suppression (TVS) in an RF connector using a surge block module (SBM)

Vinay Budhraja, Kyle Gobble, Justin Bahaj, Stephen Crabtree, Richard Johannes; Application serial no. 62/988,029

-Miniaturized polymeric probes for contact applications

Vinay Budhraja, Vishal Musaramthota, Eric Hallstrom, Jed Bentz; Application serial no. 62-82,108,050

-Silver-max-phase composite coatings and methods of depositing the same

Vinay Budhraja, Vishal Musaramthota, Eric Hallstrom, Jed Bentz; Application serial no. 62/872,244

-Twisted Detwisted springs for probe applications

Jarvis Stirn, Vinay Budhraja, Dave Sanders; to be submitted

INDUSTRIAL PRODUCTS

-Spring Probes

Tried advanced gold plating materials like Xtalics, Nanodiamond gold, Laser gold, anti diffused gold, dual nickel dual gold for spring probes to find best solution of gold hardening

Fabricated and assembled spring probes using polymer. Company filed patent of this technology

Proposed silver maxphase plating for spring probes. Company filed patent of this technology

Designed twisted spring to improve yield and to reduce manufacturing cost. Company filed patent of this technology

-Connectors

Designed and assembled 38999 connectors for defense applications

Designed ARINC connector for space applications

Designed PCB connector system for protection against lightening strike and high electromagnetic radiation. Company filed patent of this technology

Designed fiber optics based connectors

-Thin Film Devices

Introduced inkjet and super inkjet technology for thin film resistors

Produced graphene based composite as substrate for thin film devices

Found alternative of copper material for heat sink applications

-Far UV Lamp

Design of experiments for testing of lamp

Managed CAD Designing and 3D printing

Funding of this project was supported by NASA

-Integrated Circuit with MOS and MOSFET

Tested the MOS and MOSFETs on Integrated Circuit fabricated by SEMATECH

Tested the MOS devices on Integrated Circuit fabricated by Rutgers

-Reflectometer for wafer processing

This equipment was patented by my mentor Dr. Bhushan Sopori. US Patent: US 200******** A1; Link: https://www.google.com/patents/US20060219678

The license of the equipment was bought by GT Solar

I created the statistics of the experimental results to compare with manual results

-Optical Processing Furnace (advances as Optical Cavity Furnace)

Links: http://www.nrel.gov/news/features/2011/1629

I designed and assembled the electrical part under the guidance of Dr. Bhushan Sopori (Principal Engineer, NREL)

This furnace was patented by my mentor Dr. Bhushan Sopori. US Patent: 5452396A; Link: https://www.google.com/patents/US5452396

This furnace won R&D 100 Award in 2011. Link: https://www.pvtech.org/news/nrel_receives_three_awards_for_its_solar_advancements_from_rd_magazine

The license of the furnace was bought by AOS Solar.

Link: http://www.nrel.gov/docs/fy13osti/59012.pdf

-PV Wafers and Devices

NSF Grant Funded in FY2015 Budget:

Link: https://www.nsf.gov/about/budget/fy2015/pdf/Entire_Document_FY2015.pdf

National Renewable Energy Laboratory, Department of Energy, Funded from July, 2008 to Dec, 2011.

Tested solar cells and wafers of various companies like MEMC Electronic Materials, Solarworld, Solexel, BP Solar, Sixtron Advanced Materials, Ferro Electronic materials, Moserbaer, BHEL India etc.

PUBLICATION SUMMARY

-International Journal: 9

-International Conferences: 24 (14 oral, 10 poster)

-Invited Talks: 6

SKILLS

Circuit/Device Simulators: HSPICE, VHDL, Device Simulators: Nanohub, PV Optics, AMPS, PCID, Afors-HET, QUOKKA, ICECREM.

Computer Language: C/C++, Matlab, Mathematica.

CAD Designing: Solidworks with animated assembly

Processing: Firing of solar cells using OPF (Optical Processing Furnace), Flat polishing of Silicon wafer, Photolithography, E-Beam Lithography, Metallization (sputtering, thermal evaporation), Anodization of Aluminium, Electroplating, Reactive ion etching, Plasma enhanced chemical vapor deposition (PECVD), RCA-1 and RCA-2 cleaning, Sintering of graphene, CMP, Oxidation of silicon, Spin coating etc. 10 years of process integration experience in cleanroom environment.

Characterization: Force deflection resistance (FDR), Lifecycle test LCT), Current carrying capability test (CCT), Minority carrier life time of silicon wafer, Diffusion length measurement using SPV, Spectroscopy for reflectance and transmittance, I-V, C-V, AFM, PVSCAN for defect mapping, LBIC (Light Beam Induced Current), Scanning electron microscopy (SEM), Spectroscopic Ellipsometry, Reflectometer for scanning of defect density and reflectance of wafers size upto 6 inch, Lock in thermography for detection of shunts and hot spots, Electroluminescence etc.

HONORS AND AWARDS

-Technology Excellence Award, Smiths Interconnect, July, 2019.

-Top Performer, Enabling Technologies team, Smiths Interconnect 2019.

-Runner up of the scientific competition at Smiths Interconnect Global called “Moonshot” Mar, 2019.

-Received Graduate Student Award from conference committee of 37th IEEE PVSC, Seattle, USA, June, 2011.

- Runner up of Best Poster Award in 34th IEEE PVSC meeting, Philadelphia, June, 2009.

- Received Graduate Student Award from NJIT to attend 34th IEEE PVSC conference, 2009.

- Received Graduate Student Award from conference committee of 209th meeting of Electro Chemical Society, Denver, Colorado, USA, 2006.

- National scholarship from Govt. of India 1995-1998.

REFERENCES

Peggy Gardella, HR, Smiths Interconnect, Kansas City KS, USA, add3g2@r.postjobfree.com, Ph: 913-***-****.

Scott Armstrong, Project manager, Smiths Interconnect, Stuart, FL, USA, add3g2@r.postjobfree.com, add3g2@r.postjobfree.com, Ph: 772-***-****.

Jarvis Stirn, Design Engineer IV, Smiths Interconnect USA, add3g2@r.postjobfree.com, Ph: 785-***-****.

PJ Piper, CEO, Far UV Technologies USA, add3g2@r.postjobfree.com, Ph: 816-***-****, 917-***-****.

Rupesh Chudasama, Additive Manufacturing Scientist, Smiths Interconnect UK, add3g2@r.postjobfree.com. Ph: +44-781*******.

Durga Misra, Professor, New Jersey Institute of Technology USA, add3g2@r.postjobfree.com, Ph: 973-***-****.

Vinay Budhraja

3450 N Ridgewood St, # 514 add3g2@r.postjobfree.com

Wichita, KS-67220, USA Ph: 816-***-****

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