Engineering Design

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MARIYA SIMON

To work in a challenging environment demanding all my skills and efforts

to explore, evolve and realize my potential where I get the opportunity for continous learning.

B.TECH, IES College Of Engineering, Chittilappilly Calicut universty,Kerala

Branch:Electronics and Communication Engineering

CGPA: 6.8, Year: 2018

12th CJMAHSS Varandarappilly

Percentage:78%, year:2014

10th Vimal Jyothi Central School,Muplyum

Percentage:90%, year:2012

Advanced VLSI Design and Verification course

Maven Silicon VLSI Design and Training Center, Bangalore Dec 2018 to till date

Bluetooth 5.0- VIP

HVL: System Verilog

TB Methodology: UVM

EDA Tool: Questasim

Description:Bluetooth 5.0 is wireless communication device with low energy, wider range and increased speed compared to previous version. Responsibilities:

Understood VIP usage

Written testcases to verify advertising PDUs,advertising, scanning and initiator filter policies,data PDU,control PDU

Synchronisation of transfer using access address and PHY Address: Manjaly house,

Varandarappilly PO

Thrissur,Kerala

pin – 680303

Mobile: +91-960*******

Email:mariyasimonmanjaly

@gmail.com

LinkedIn ID:

www.linkedin.com/in/mari

ya-simon-850613159

HDL:Verilog

HVL:System verilog

Methodology:UVM

RTL Coding

Code Coverage

Assertion based

verification

Functional

Coverage

C, C++

A paper based on the project ”Virtual Reality Fire Fighting Robot” was published in International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREECE), Volume 6, Issue 2, February 2018.

PROFESSIONAL QUALIFICATION

CAREER OBJECTIVE

EDUCATIONAL QUALIFICATION

PUBLICATION

VLSI PROJECTS

SKILLS

CONTACT

UART- IP Core – Verification

HVL : SystemVerilog

TB Methodology: UVM

EDA Tools: Riviera Pro - Aldec

Description: The UART IP core provides serial communication capabilities, which allow communication with modem or other external devices. UART will operate in – Simplex, Full Duplex mode and loopback mode. Responsibilities:

Architected the class based verification environment in UVM

Defined Verification Plan

Verified the RTL module using SystemVerilog

Generated functional and code coverage for the RTL verification sign-off Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Riviera Pro -Aldec and ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Responsibilities:

Architected the block level structure for the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design.

ENGINEERING PROJECT

Virtual Reality Fire Fighting Robot

The main objectives of our work are to provide information concerning fire incident and how to deal with the critical situation as realistic as possible.

Roles and responsibilities: Played key roles in the design and implementation of circuit, and in writing codes in python, performed different commands for the robotic vehicle and also in the whole assembling activities. AHB2APB Bridge IP Core Verification (Internship project going on) HVL: System Verilog

TB Methodology: UVM

EDA Tool: Riviera Pro – Aldec

Description: The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses.

DECLARATION

I hereby declare that the above mentioned information are true to my knowledge. Place:

Date: signature

(Mariya Simon)

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