**** ******* ****

Garland, Texas *****

972-***-**** (cell)

972-***-**** (home)

add06s@r.postjobfree.com

Peter J. Cavezza Jr.

Objective

Summary of Qualifications

Lead Electrical Engineering related position with a progressive organization where I can contribute my experience and strong technical background as an Electrical Engineer, digital circuit and board designer. An opportunity to continue to develop with challenging responsibilities where I can contribute to an organization’s sustained profitable growth.

A skilled, responsible Lead Engineer and Team Member with extensive design and troubleshooting experience in the Electronics industry. Demonstrated strong technical background in Digital Design and test, specifically digital board design. A team oriented, open and honest communicator who builds strong customer relationships and inspires trust, confidence, and loyalty with empowered employees.

Professional Experience

1995 - 2018 Raytheon Company McKinney, Texas

Senior Electrical Engineer II

IPT Lead & Lead Electrical Engineer for the Processor, Interface Controller and Communications PICC 2.0 and PICC 3.0 module for the F22A Raptor. IPT Lead and lead engineer of one Electrical Engineer. Earned Value Management (EVM) Level 1 & Level 2 certified, R6Sigma Specialist. Detailed board redesign, project production lead and lead engineer for Customer Returns. Program Property Manager (All PICC programs) for customer property and generation of Property Management and Intellectual Property plans. Acting PICC 2.0 Systems Engineer. Lab Manager for Joint Strike Fighter Program.

Digital and Cable Design for use within the Tracer System and Tracer test equipment. Digital board design included video type devices.

Optical Receiver circuit and FPGA controller design, test and integration for use within a MEMS array. Demonstrated capabilities of controlling the MEMS with a Logic Analyzer Pattern Generator for use on the 10K Array (Airborne antennae array) project.

Power Supply subsystem definition, equipment selection and requirements needed to power the payload used for the HALOStar ( Flying cable link platform) aircraft proposal.

Redesign of Optical to Electronic OC-1 and OC-3 Tele Communications Boards, Defined Test Procedures for checkout and acted as Drawing Control Coordinator. Design and fabrication coordinator of two Digital/ Analog designs, plus drawing configuration.

Digital design of two boards for Low Cost Cruise Missile Defense (LCCMD). Design of motherboard used for power, RF and signal distribution. And an Array Control Interface board used for controlling a Beam Steering Controller. Both designs were finished on time and under budget.

Design, Test, Board Fabrication Coordinator and Drawing Control of eight different digital designs for the Integrated Sensor Systems (ISS) Demo Configuration. The designs utilized various technological platforms; two sided surface mount boards in the form of Integrated Product (IP) modules, VME, PCI, CAN bus and various FPGA's.

Lab coordinator and Test Equipment manager for multiple systems.

1986 - 1995 Lockheed Martin Corporation Moorestown, NJ

Senior Member Engineering Staff

Design, integration, test and customer sell off of the microprocessor controlled AEGIS SPY-1B/1D Radar Signal Processor.

Supervised and performed the design analysis for system failures occurring on the SPY-1B/1D signal processors. This involved determining the problems (software, hardware (Digital or RF) or firmware), defining a solution and incorporating the solution. This effort also entailed making critical changes to the weapons specification. Acted as Cost Account Manger for the $6.43 million program, including labor scheduling and cost control for all levels of engineering support necessary for production and test integration. All systems were delivered on time and under budget.

1983 - 1986 Texas Instruments Inc. Dallas, Texas

Digital Design Engineer

Design integration, test of an Interface Subsystem for the Data Flow Signal Processor (DFSP). The design utilized PALS, PLAS and a 16-bit microprocessor and interfaced with a VAX 11-780 via an IEEE-488 bus network. Supervised the design implementation of a Cycle Redundancy Check Generator used in the Monitor Subsystem of the DFSP.

Education

BS/ Electrical Engineering

Southern Methodist University

AS/ Electrical Engineering Technology

Pennsylvania State University

Professional Memberships

State of Texas Licensed Professional Engineer (Expired 2017)

Awards received

Air Force Commendation Medal (2), AEGIS Excellence Award, AEGIS Employee Recognition Award, AEGIS Superior Team Achievement Quarterly Award (3), Angel Team Excellence Award for Demo Team (2), PICC Team Excellence Award for Underfill Milling Team.

Corporate Trade Secret (Team Member)

Security clearance

Secret