*** ***** ******, ******* ****, California
Systems Engineer with more than 30 years in hardware/ASIC/IP design, hands on, architecture and verification experience. Expertise in Verilog design. Expertise in C/C++ in both embedded and application environments. International project and team management. Proven ability to perform and excel in diverse cultural environments as a participant and leader. Subject Matter Expertise in RFID. Expertise in chip and system level verification. PROFESSIONAL EXPERIENCE
Senior Manager R&D, Zume Inc, CA. April 2019 – April 2020
• Managing Critical R&D Projects for Zume Pizza. Projects ranged from IoT, to Food Truck Battery, tracking of prepared food items. RF and control system
• Managed a staff of 6 engineers. Successfully managed the first companywide program across most engineering disciplines. Managed small electrical R&D team. EVP Engineering, Lab Sensor Solutions, CA January 2014 – Present
• Founder of LSS, responsible for all Engineering tasks and processes. From concept through manufacturing of both hardware and software systems. Management of Engineering team of senior staff (both hardware and software). Design of BTLE IoT temperature solution for tracking medical samples during transport. Product has expanded into other verticals as well. Sr. Staff Engineer, Ion Torrent S. San Francisco, CA 2011 – December 2013
• Created Wafer Sort test capability, saving the company in excess of $500K/quarter. Created hardware, software, and firmware for Gui Generate testing system Director of System Engineering, Tagent Corporation Mountain View, CA 2006 – 2011
• Developed all System Hardware and Software for Tagent’s RFID solution. This included an UWB Reader, a 5.8GHz transmitter, and DSP firmware. This included Hardware and Software development. Team Leadership of 5 engineers Director of Software Engineering, Applied Wireless ID Group (AWID), Morgan Hill, CA 2005 – 2006
· Architected, developed and lead team creating first Software Defined RFID Reader. Managed a team of 6 engineers plus contractors.
Director of Systems and Protocols, Intelleflex Corporation, Santa Clara, CA 2004 – 2005
· World Class Gen2 Class 3 RFID system. Team Leadership Contractor, Virtual-Silicon, Sunnyvale, CA. 2003
· Test Chip Development and debug
Sr. ASIC Designer, Xerox Corporation, Impact Group, Palo Alto, CA. 1999 – 2002
· Successful image path chip development for copier systems Daniel Paley
519 Grand Street, Redwood City, California
Principal Engineer, Manager, Project Lead., Phoenix Technologies Ltd., Virtual Chips Division, San Jose, CA. 1998 –1999
· Development and leadership for Firewire project. Team Leadership in international setting. Project Leader, Design and Verification Vadem. San Jose, CA. 1995 – 1996.
· Managed the successful completion of the VG330, an SOC microcontroller. Team Leadership.
Member of Technical Staff, Rambus Inc., Mountain View, CA. 1991 – 1995.
Design Engineer, Olivetti Networks and Systems, Standard Platform Division, Menlo Park, CA. 1989 – 1991.
Design Engineer, CAE Link Flight Simulator Corporation. (Formerly Singer Link Flight), Advanced Products Operations, Sunnyvale, CA. 1986 – 1989. EDUCATION
Bachelor of Science, Computer Engineering. University of the Pacific, Stockton, CA. May, 1986.
6,457,152, Device and Method for testing a device through resolution of data into atomic operations. Granted Sept 24, 2002.
7,612652, Battery Activation Circuit. Granted Nov. 3, 2009 7,646300, Master Tag. Granted Jan. 12, 2010
7,818,572 Security system and Method. Granted October, 2010 8,248,211 Selective RF Device Activation. Granted August 21, 2012 8,249,251 Security System and Method. Granted August 21, 2012 8,674,809 Selective RF Device Activation. Granted March 18, 2014 9,071,447 Security system and method. Granted June 30, 2015 9,407,445 Security System and Method. Granted August 2, 2016 5 additional patents filed in the area of RFID and Bluetooth.