AJEETH KUMAR S R
Phone No:+91-989******* firstname.lastname@example.org
To work in an organization that brings the best out of me in information & technology sector and to utilize my analytical and problem solving capabilities for organizational and professional development.
B.E in ELECTRONICS
K.L.N. COLLEGE OF ENGINEERING
(ANNA UNIVERSITY AFFILIATED
THAIGARAJAR MODEL HIGHER
SECONDARY SCHOOL( TN STATE
THAIGARAJAR MODEL HIGHER
SECONDARY SCHOOL (TN STATE
VLSI DOMAIN SKILL:
HDLs : Verilog
HVLs :System Verilog,UVM
TOOLS USED :Questasim, Modelsim
AREA OF INTEREST:
1) SMART WHEEL CHAIR
Objectives : This is a Developed for Physically challenged people Technologies Used: arduino and sensor
2) Earth Worm- A Friend of Farmer
Objectives: It can diagnose multiple diseases of a plant by analysing the leaves of that Plants .For now, we have trained our model with 17 diseases of 3 different plants. Technologies Used: Artificial Intelligence that built using Inception v3 neural Network model
FINAL YEAR PROJECT
3) Design and fabrication of wireless controller terrain rough vehicle Objectives : To detecting a human in disaster area Technologies Used: PIC Controller, sensor, ZIG-BEE, Microsoft Visual Basics CURRICULUM PROJECT
Design & Verification of Asynchronous FIFO using Verilog(Tool: ModelSim) Asynchronous FIFO is used to connect components transmitting and receiving at different frequencies. I have developed RTL code and functional verification of the same using Verilog.
Developed AXI VIP and validated its behaviour using AXI SLAVE.
Advanced Extensible interface is a family of AMBA specification. The AMBA AXI protocol supports high-performance, high-frequency system designs .It supports BURST Transaction, Aligned and unaligned transfers .I have developed AXI VIP and validated it behaviour with AXI SLAVE.
Development of AHB Protocol using System Verilog(Tool: Questa Sim) The Advanced High-performance Bus (AHB) is used for connecting components that need higher bandwidth on a shared bus. These could be a internal memory or an external memory interface etc. but the shared bus would limit the number of agents. Protocol also support the features like burst transfer, split transactions etc. which improve its performance. I have developed Test bench for these and tested on AHB slave.
Memory Controller Functional Verification using System Verilog(Tool: Questa Sim) Design supports SDRAM, SSRAM, Flash & Synchronous Chip select devices. It has support for 8 chip selects. It also supports flexible timing configuration for different memory types. As part of this design verification, we created test bench using SV to generate scenarios targeting all types of supported memories for different possible combinations & different sizes supported. We also developed monitor, reference model
& checker as part self-checking test bench implementation. LANGUAGE KNOWN:
Tamil, English, Sourashtra
FATHER’S NAME : S.V.Rajendran
OCCUPATION : factory in charge
DATE OF BIRTH & AGE : 28-08-1997 & 22
GENDER : Male
NATIONALITY : Indian
I hereby declare that the above-mentioned information is correct up to my knowledge and I hear the responsibility for the correctness of the above-mentioned particulars. DATE :