Andy (Hai) T. Vu

**** *. ********* **

Anaheim, CA. 92806

Phone: 818-***-****

Email: adcx6a@r.postjobfree.com

Objective

Seeking to apply strong background and several years of hardware and software experiences for a hardware engineer position.

Hardware and Software Designs Tools:

1. Altium 2015 schematic capture and PCB layout.

2. Agilent ADS for high speed channel simulation.

3. Verilog/VHDL design/simulation using Xilinx ISE and ModelSim. 4. Use C/C++, C#, COM, and Visual Basic within Microsoft Visual Studio to develop GUI tools. 5. Develop and perform software regression tests and test units. 6. Operating systems: Windows, Microsoft Office Tools. PROFESSIONAL EXPERIENCE

House of Batteries – Provide Lithium-Ion Battery Electronics Solutions Nov. 2015 – 2019 House of Batteries manufactures electronic components to manage Lithium-Ion rechargeable batteries. The products consist of electronics boards and complete ready-to-be-used batteries assemblies ranging from 1A – 100A of current.

Senior Engineer: Develop hardware and firmware for battery management systems.

Design hardware and software architecture.

Specialized in designing low current consumption circuit boards during idle for Lithium-Ion batteries. The current consumption is within 50uA during idle to save batteries energy.

Using Keil uVision to develop firmware to manage batteries protection circuits using low power uController STM32L0 family from STMicroElectronics. Develop firmware using various bus: I2C, CAN bus, and RS-232 to interface batteries management system with other devices or external systems.

Personally revamp the entire company test automation system. Design both software and hardware to speed up final battery testing before shipping to customers. Improve shipment by 20%. BROADCOM CORP . – DEVELOP HIGH SPEED ETHERNET/BROADBAND IC April 2005 – Feb 20015 SENIOR STAFF HARDWARE/SOFTWARE VALIDATION AND TESTING ENGINEER

Oversee all GPHY Gbe SERDES testing for Ethernet application devices. Lead DVT engineer and serve as lead contact for design/application/marketing.

Lead testing effort from design stage to testing completion to successful mass production.

Provide recommendations in board design to improve Multi-GbE SERDES device performance in areas such as high speed signal routing, minimizing components in signal paths, good reference clock design to achieve low phase noise, proper power supplies filter design, and proper usage of ground vias to improve ground return current and in turn reduce noise and cross-talk.

Perform DVT (Design Validation Test) for GPHY SERDES devices that operate at 1.25G, 5.0G, and 10.3125G data rate.

Develop test plans and procedures for multi-gigabit SERDES to meet IEEE standards.

Finding solutions for board design issues such as ground noise, power supply filtering, sensitive differential signal layout.

Have extensive knowledge of test equipment: Agilent JBERT, DCAJ, Spectrum Analyzer, VNA.

Using C++ and Windows MFC to develop graphical user interface for high speed SERDES testing and characterizing SERDES transmit/receive signal jitter and noise and analyzing periodic jitter using Bessel equations. Test solutions can be run overnight with minimal manual involvement.

Use WinPcap to develop GUI-based test suits for Ethernet GPHY devices. Program can be controlled manually or automatically through RS-323 port. Tests are carried out by transmitting and receiving ethernet packets over CAT5 or Fiber cables and monitored for errors. Programmed then verified and tested using WireShark software.

PETTA TECHNOLOGY May 2004 – April 2005

Hardware Engineer: Develop Embedded Hardware and Testing Solutions.

Use Protel DXP 2002 to design MicroController board using Atmel AVR ATMega8535. Use off- the-shelf IC as glue logics to implement real-time tracking, LCD display, external keypad input, and data storage. MicroController board communicates with PC via USART Port. Provide test strategies for MicroController board.

Provide consultation in testing Soil Resistance Measurement device for industrial applications using discrete components such as Opamps, Relays, Diodes, IC power supply controllers. Provide hardware/software test solutions for interfacing analog board to MicroController board.

Supervise embedded firmware testing and development for MicroController board. TERADYNE, VLSI Test Equipment Division Mar 1998 – April 2004 Development Engineer: Develop Software and Test Strategies 1999 - 2004 Develop and implement high level hardware and software to characterize, calibrate, and test Teradyne test equipment J973 for timing and dc level accuracy running in excess of 400Mhz using latest Tektronix and HP test equipment. J973 is Teradyne’s highest performance tester aiming to test high-end processors such as the Intel Pentium, AMD Athlon and Motorolla Power PC. Develop test procedure and strategies to test floor production to enable on-time shipment.

Study schematics and take into account system parameters to develop software to characterize and test digital boards and provide test coverage to ensure quick board bring-up and shorten production time.

Develop software to characterize and test for 200A switching power supplies to meet DC and Timing requirement for microprocessor testing.

Develop TDR techniques and related hardware to measure transmission line and long coaxial cable time delays. These techniques enable our testers to meet very stringent specs, within +/- 100 pico seconds of accuracy for testing Intel and AMD high-end processors.

Develop C++ programs to calibrate and test all system DACs using gain and offset to improve DC and Timing accuracy.

Collect data from subsystems to establish system specs.

Develop test and bring-up procedure and responsible for training production test personnel’s.

Develop software in C/C++, COM, and Visual Basic to perform the following functions: 1. Automatic data acquisition via GPIB bus using Tektronic and HP test equipment 2. Provide user interfaces to interact with the Teradyne tester. 3. Calibrate Teradyne test system to meet all DC and Timing requirements. Teradyne VLSI Applications Engineer 1998 - 1999

Using Teradyne IG900 software, provide test software solutions to reduce bugs and improve reliability for customer software. Develop test strategies and solutions for customer IC’s. Characterized and improve customers test dibs (fixture) to help improve device yield. Specialized in testing high speed (400 MHz) and high end devices such as Rambus Controller ASIC cell, AMD Athlon devices.

Characterized RAMBUS Controller ASIC Cell for setup/hold time, Tq Output Window under different frequencies (up to 400Mhz). Performed noise simulation on ASIC cell to understand how Rambus parameters were affected under application environments.

Characterized test equipment accuracy and made improvemens in order to give the best yield to AMD K7 and Rambus devices with respect to such parameters as operating frequency and setup/hold time.

Develop application notes and documents with regard to using Teradyne J973 Tester. INTEL CORP. Sep 1995 - Mar 1997

VLSI Engineer – Physical Designer

Assisted the Floating-Point Group in designing a floating-point unit for the Intel Merced processor. Provided VLSI knowledge in circuit design/physical design trade-off. Designed physical and floor planning that optimized for speed, robustness in areas such as noise tolerances, electro migration, efficient use of silicon space, and reliability.

Summary of skills and experiences:

1. Custom design of CMOS static and dynamic circuit. 2. Circuit layout to optimize speed, reliability, noise tolerances, and area. 3. Optimal pipeline design to improve overall speed. 4. Circuit simulation using SPICE-based simulator from Cadence. EDUCATION/ACADEMIC BACKGROUND

CAL STATE POLYTECHNIC UNIVERSITY - California 1990 - 1995 B.S. DEGREE IN ELECTRICAL ENGINEERING

GPA: 3.28

Contact this candidate