Process Development/Manufacturing Engineer
Resume:
Mark D. Mc Nicholas
Gilbert, AZ 85295
Email: adcs8h@r.postjobfree.com
www.linkedin.com/in/mark-mcnicholas-bb35a756/
Summary
Proven process engineer of over 30 years’ experience, having installed systems and processes globally, as well as having designed/implemented system upgrades and conducted training for both process and equipment engineers.
Accomplishments
Instituted new physical vapor deposition process definitions and flows for mainstream interconnect, MEMS, inkjet, bulk acoustic wave/piezoelectric, thin film resistor, superconducting quantum interference devices, packaging, and optical applications (OEM, AMAT, TEL, MRC) at semiconductor wafer fabrication facilities globally.
Resolved process development, process transfer, device integration issues, equipment hardware and system related issues for MRC Eclipse, AMAT Endura, and SFI Endeavor PVD systems (OEM, AMAT, TEL, MRC).
Developed thin wafer handling hardware and process techniques for the MRC Eclipse Mark IV, down to 100 um thin substrates (50 um Taiko) (OEM) to minimize thin film stress and wafer bow.
Designed a DC bias upgrade for the MRC Eclipse Mark IV (OEM).
Developed a RF sputter chamber configuration for the AMAT Endura (OEM) and for the MRC Eclipse Mark IV (TEL).
Integrated a DC Pulse upgrade into all MRC Eclipse Star/Mark II/Mark IV systems (OEM) to allow sputter deposition of non-conductive films.
Released a RF diode etch package for the MRC Eclipse Mark IV (TEL).
Retained employment through 1 corporate consolidation/relocation (Materials Research Corporation) and 4 corporate acquisitions (Tokyo Electron Ltd – OEM Group Inc).
Received award for 3-member team role in successful sale of Legends business unit from Applied Materials to OEM Group (AMAT).
Responsible for system sales of $3.2M based on technical proficiency (OEM).
Received Applied Materials Equipment Renewal Services “Team of the Quarter Award”, Q3, FY07 for developing a new thin film resistor process which maintained an installation base of 11 MRC Eclipse systems.
99% success rate on customer sample demonstrations since 1997.
Experience
Assist in system field installations (Tiers I, II, III), preventive maintenance, equipment troubleshooting, process qualification, manufacturing/process/equipment engineer training, and technical support functions across semiconductor wafer fabs globally (OEM, AMAT, TEL, MRC).
Assist Engineering team in assessing hardware modifications, new design layouts, and sustaining functions across all physical vapor deposition products (OEM, AMAT, TEL, MRC).
Assist Product Management and Corporate Marketing on product presentations and sales datasheets (OEM, AMAT, TEL, MRC), as well as product training to the sales team.
Provide review of new system order and upgrade Requests for Quote and Non-Disclosure Agreements for technical and logistical response back to customers for Materials Research Corporation Eclipse and Applied Materials Inc Endura product lines (OEM, AMAT, TEL, MRC).
Perform industry market analysis of technology trends and developments, provide feedback to Sales, Marketing, and Product Management teams, and determine ability of existing product offerings to compete in new applications (OEM, Metron, AMAT).
Assist Product Management and Engineering teams in bill of material generation for new and refurbished system builds, as well as system upgrade offerings (OEM, AMAT, TEL, MRC).
Experience in DC, DC Pulse, RF, AC, and Reactive Sputtering.
Experience with cryogenic, turbomolecular, and diffusion pumped vacuum systems.
Metrology experience includes 4-point probes (CDE, Prometrix), profilometry (Tencor, Dektak), stress measurement (Flexus, FSM), spectrophotometry/ellipsometry (Nanometrics, Filmetrics, Prometrix, Gaertner-Scientific), XRF (Rigaku).
Sole provider of global PVD field process support since 2008.
Sole provider of MRC Eclipse applications laboratory process documentations since 1997.
Assist Technical Support on customer parts/equipment/process related daily issues.
Versed in Statistical Process Control, Design of Experiments, FMEA and 8D techniques (MRC, CSC).
Positions Held
Senior Applications Specialist
OEM Group LLC; Gilbert, Arizona; August 2008 – February 2020.
Applications Laboratory Manager
Applied Materials, Inc; Gilbert, Arizona; December 2004 – August 2008.
Metron Technology; Gilbert, Arizona; September 2003 – December 2004.
Tokyo Electron Arizona, Tokyo Electron Limited; Gilbert, Arizona; March 2000 – September 2003.
Senior Process/Applications Engineer
Tokyo Electron Arizona, Tokyo Electron Limited; Gilbert, Arizona; February 1998 – March 2000.
Materials Research Corporation; Gilbert, Arizona; June 1997 – February 1998.
Materials Research Corporation, Sputtering Systems Division; Orangeburg, New York; July 1994 – June 1997.
Process Engineer
Cherry Semiconductor Corporation; E. Greenwich, Rhode Island; November 1989 - July 1994.
National Semiconductor Corporation; Danbury, Connecticut; July 1988 - November 1989.
General Instrument Corporation; Hicksville, New York; January 1987 - June 1988.
Education
Massachusetts Institute of Technology, Bachelor of Science - Chemical Engineering.
New England Institute of Technology, Associate of Science - Electronic Technology.
Patent
“Universal Backplane Assembly and Methods”; U.S. Patent No. 6,645,344 B2; Granted November 11, 2003.
Publications
“Plasma Charging Effects on Device Degradation from Via Sputter Etch”, SPIE (Society of Photo-Optical Instrumentation Engineers) Microelectronic Device and Multilevel Interconnection Technology Conference.
“Microstructure and Reliability of Sputter Deposited Cr-CrCu-Cu Thin Films for Flip Chip Applications”, MRS (Materials Research Society) Meeting,
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