FRANK MATSUMOTO

*** ********* **., *** ******, CA 92078

858-***-****, adclot@r.postjobfree.com

Summary

● 15+ years work history as an FPGA engineer in product development and support

● Extensive experience in design, verification, hardware test and debug

● Excellent project management skills, problem solving skills and a team player

● US citizenship currently residing in the San Diego, CA area Skills

● FPGA: VHDL, Verilog, System Verilog, Xilinx, Altera, Intel

● Devices: Spartan, Virtex, Kintex, Ultrascale, Ultrascale +, Zynq, Arria

● Technologies: PCIe, DMA, TCP IP, Ethernet, MAC, SPI, AXI, Camera Link

● Tools: Vivado, ISE, Chipscope, ILA, SDK, Modelsim, Questasim, Quartus

● Software: C,Python, Linux, vim, bash, tcl, svn, JIRA, GitLAB, AWK

● Multilingual: Native English, Business Level Japanese (JPLT2) Experience

Macnica Americas - Solana Beach, CA FPGA Engineer - 2017.03~2020.03 FPGA development tasks such as RTL design, verification, hardware test and debug. Technologies included Kintex Ultrascale, Zynq and Arria devices.

● PCIe DMA RTL design, verification, regression test, debug, performance characterization

● SMPTE 2022 FEC engine debug using QuestaSim verification and Python modeling

● Xilinx Tandem with Remote Updates development

● ProAV Zynq video transport hardware testing

● Japanese customer support requiring bilingual interfacing Nomura Securities - Tokyo, Japan FPGA Engineer - 2010.11~2017.03 Developed and maintained Low Latency Trading platforms for High Frequency Trading clients. Hardware related tasks include RTL design, verification, hardware test and debug. Technologies included Virtex 6 & 7 devices. Other tasks include Python and C programming. FPGA Sub-microsecond low latency Arrowhead/OUCH risk check platform.

● RTL TCP/IP packet generator with multi-session/checksum calc/throttling targeting Virtex 7 FPGA

● RTL Nanosecond timestamper targeting Virtex 7 FPGA

● Tamba Networks 3rd party Low Latency MAC IP Virtex 7 integration

● 3rd Party Virtex 6&7 board evaluation and integration

● FPGA RTL development: 8:1 ethernet serialization, SPI, risk check

● Python object oriented pcap parser for real time connectivity and trade monitoring dashboard

● Multi-Threaded Python ArrowHead/OUCH client/exchange simulator

● C maintenance of tunnel/utility programs

Xilinx - Tokyo, Japan Application Engineer - 2004.03~2010.08 Provided Engineering Sales support for FPGA customers such as Fujitsu, Canon, and Toshiba. Projects include device qualification, Pre-Post Sales support including key technologies like LVDS, Memory Interface, High Speed Serial Interface and general FPGA technology. This support resulted in multi-million dollar design wins. 2

Pre-Post Sales Support included customer visits to understand business opportunities and needs, and created proposals and feasibility studies to meet those needs in pursuit of design wins. Created custom designs to meet specific customers requirements. Onsite troubleshooting and liaison between Japan and US when required. Qualified Virtex-4 at Fujitsu. Qualification required heavy liaison between Fujitsu and Xilinx (USA) requiring bilingual skills. Countless customer meetings, presentations and negotiations required. Qualification resulted in Fujitsu corporate-wide usage of Virtex-4 and multi-million dollar revenue for Xilinx. Also created a basis for future qualification of Virtex-5 and Virtex-6.

Bussan Micro - Tokyo, Japan Application Engineer - 2002.04~2004.04 Engineering Sales support for graphics scaler chip (Oplus). Made customer visits, presentations and product demonstrations to promote the product portfolio. Customers include panel and projector makers such as Sanyo, Hitachi, Sony, Toshiba, Pioneer, etc. Also required bi-lingual liaison between Japan and Israel. Triple One - Tokyo, Japan Digital Design Engineer - 2000.04~2002.04 Contract design engineer for customers including NEC, Mitsubishi and Toshiba. Provided simulation and design support on a project basis. Projects included glue logic macro development and design confirmation simulation. Used VHDL, Verilog and Modelsim, and UNIX environment.

Tokyo Electron - Austin/Portland, USA Process Engineer - 1997~2000 Worked as field engineer and process engineer for oxide etcher group in R&D and production environments. Responsibilities included field engineering support for a 300mm Etcher demo at Sematech, process support of development and production including, and liaison with Japanese laboratory/factory in Japan by email, phone and travel.

Kanazawa Industrial University - Ishikawa, Japan Teaching Assistant - 1995~1997 Assisted the development of an undergraduate engineering design curriculum for the university. Responsibilities included liaison between Japanese staff professors and foreign visiting professors, translation, and creating lecture materials and conducting lectures in Japanese.

Watanabe Giken - Fukushima, Japan Development Engineer - 1994 ~1995 Developed new technologies for a precision sheet metal stamp and die manufacturing company. Responsibilities include design and development of mechanical equipment using CAD systems. Airfoil Impellers - College Station, Texas Application Engineer - 1992~1993 Provided CAD support for an axial air moving equipment manufacturer during college studies. Responsibilities included mechanical drawing creation and update, and liaison between fabrication and sales team. Education

Texas A&M University - College Station, Texas

Bachelor of Science 1993, Mechanical Engineering

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