UJJWALA

PRASAD N

B.E in Electronics and Communication Engineering

Vishvesvaraya Technological University

K.S.School of Engineering and Management

65.2%

2018

12th(PCMC)

Karnataka Pre University

Jnana Sweekar PU College

86.77%

2014

10th

SSLC

Sri Kumaran Children's Home

90.88%

2012

adcht5@r.postjobfree.com

903-***-****

https://www.linkedin.com/in/ujjwala-prasad-n-

a66b72195

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LinkedIn Id

To begin a career that offers opportunity to apply my skills and knowledge in VLSI industry and to grow as a competent professional.

Career Objective

Education

Maven Silicon Softech Pvt Ltd

VLSI Design and Verification

September 2019 - Till date

Technical Skills

HDL : Verilog

HVL : System Verilog

Verification Methodology : UVM

EDA Tool : QuestaSim,Xilinx-ISE

Knowledge : RTL Coding,FSM based

design, Simulation,Code Coverage, Synthesis,

Functional coverage,Assertions

VLSI Domain Skills:

Other Programming Skills:

C Programming,C++,VBA Coding

Professional Summary

Professional Training

Monomikai Activity for Brush holder, rivet and

solenoid switch assembly

IMDS co-ordination with concerned suppliers for

Ford, Suzuki, FCA and JD projects.

Preparation of ICL for NISSAN, M&M and ISUZU

projects for all new components.

PPAP Documentation, Verification and completion

till uploading into SAP of Srimukha, Electromags

and Ibex.

PUQ lab activities: MSA for Quality measuring

devices, layout inspection and regular inspection of incoming child parts.

Development and Implementation of Automatic

tracking of Supplier Certification status using VBA codes.

12 months of experience in SEG Automotive India Pvt Ltd(Formerly known as Robert Bosch Starters and

Generators India Pvt Ltd) as a Graduate Apprentice Trainee.

Work involved:

Router 1x3 - RTL Design and Verification

HDL : Verilog

HVL : SystemVerilog TB

Methodology : UVM

EDA Tools : Questasim and ISE

Description : The router accepts data packets on

a single 8-bit port and routes them to one of the

three output channels

channel0,channel1,channel2.

HVL : System Verilog

TB Methodology : UVM

EDA Tools : Questasim

Description: The UART IP core provides serial

communication capabilities, which allow

communication with modem or other external

devices. UART will operate in three different

modes – Simplex mode, Full Duplex mode and

loopback mode.

VLSI Project:

1.

2.UART-IP Core - Verification

Engineering Project:

Design and Implementation of Automatic Gun Turret

System.

Description: It is a portable weapon system using

Image Processing to be used mainly for motion

detection of human beings by using a web camera.It captures images and shoots at the target when it

detects motion.

BSNL - RTTC,Mysuru

Advanced IP Networking

Project Work

Internship

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge.

Date:

Place: Signature

gjaka

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