Naveen Subramanian

+Houston, Tx (346-***-**** *adcg3l@r.postjobfree.com

https://www.linkedin.com/in/naveen-subramanian-0410388b/

EDUCATION

University of Houston, Texas, USA May 2020 (Expected)

Master of Science in Electrical Engineering GPA: 3.715/4.0

Relevant Courses: Advanced Digital Design Advanced Computer Architecture VLSI Design

CMOS Analog Integrated Circuits Advanced Microprocessor Systems IC Engineering

Courses at RICE University: Advanced VLSI Design Advanced Digital IC Design

Anna University, Thiagarajar College of Engineering, Madurai Aug 2013 - May2017

Bachelor of Engineering in Electrical and Electronics Engineering GPA: 9/10

SKILLS

EDA Tools: ModelSim Altera Quartus Questasim Xilinx Vivado Cadence Virtuoso MATLAB Simulink

LTSpice System Generator HSPICE LabVIEW Linux

Programming: Verilog/VHDL System Verilog SV UVM C C++ Perl Python

Network Protocols: AMBA AXI AMBA AHB AMBA APB PCIe SPI I2C

RELEVANT PROJECTS

Design and Verification of AXI Protocol Skills: System Verilog Tool: Questasim June 2019

-Developed the AXI – Verification IP Architecture, that contains the behavior of both the master and the slave.

-Implemented verification for three write phases and two read phases, burst transactions, out of order transactions, etc.

-Created AXI - VIP components and then integrated the Master VIP with the Slave. Performed Regression and validated using coverage criteria.

Developed UVC for AHB Protocol using UVM Skills: System Verilog, UVM Tool: Questasim Mar 2020

-Developed Universal verification component Architecture that is compatible with both Master and the slave behavior.

-Created Components such as Driver, Sequencer, monitor, functional coverage, AHB Agent, UVC Configuration, Interface, Sequence item.

-Performed Validation for the same using the AHB slave model. Created cover points for specific control signals and generated UCDB files.

Implemented APB Testbench Skills: System Verilog, UVM Tool: EDA Playground Feb 2020

-Developed APB Testbench components for APB Bridge – Master and parameterized the components to be of type APB transactions.

-Created components such as Master Driver, Sequencer, Monitor, configuration, agent, environment, test and interface.

-Observed the transactions and checked whether the transaction from the driver and the monitor are the same.

Circuit Optimization with Perl Scripts Skills: Perl Scripting Tool: HSPICE Oct 2019

-Created Perl Scripts to run the DCVS circuit in HSPICE and then to parse the result from the .mt0 generated during the circuit simulation.

-Implemented optimization through the feedback loop by repeatedly changing the size of the transistors to find the lowest average delay.

-Used the linear search algorithm for optimization and then created a MATLAB compatible text file for post-processing the parsed data.

-Simulated the DCVS circuit at the end with the transistor parameters corresponding to the lowest average delay (5.81e-11).

FPGA Design of Linear System Solver Skills: SOC Integration, FPGA Emulation Tool: Xilinx Vivado Dec 2019

-Developed 4x4 Linear System Solver for 4 equations with 4 variables using Xilinx System Generator, Vivado and implemented on Xilinx ZedBoard.

-Accelerated the Given’s rotation algorithm using system generator and then matrix multiplication is implemented using the systolic architecture.

-Performed Soc integration after generating IP Catalog and executed back-substitution in the ARM core using the C++ code in Xilinx SDK.

-Improved the performance by reducing the Utilization of DSP to 15% and I/O usage is made null by using AXI-lite interface across I/O ports.

Design of 16-bit RISC Processor Skills: RTL Design, Verilog Tool: Modelsim Jan 2019

-Designed a 16-bit RISC processor using Verilog and simulated the modules for processor data flow.

-Created modules like ALU, Control Unit, Instruction Memory, Data Memory, MAC etc. for RISC processor along with UART Feature.

-The testbench for this design is created and the design is verified using ModelSim.

PROFESSIONAL EXPERIENCE

Teaching Assistant Company: University of Houston, Houston Aug 2019 – Present

-Teaching undergraduate students to perform lab experiments in Digital Design and Microprocessor Architecture using Intel Altera FPGA.

-Instructing students in their experiments, final projects and familiar with a logic analyzer, oscilloscope, function generator, etc.

ASIC Design Verification Intern Company: SOCDV Technologies Private Limited, Bengaluru May 2019 - July 2019

-Performed functional verification of the memory controller (supports SDRAM, SSRAM, FLASH, ROM) using System Verilog.

-Created the test plan for verifying various features in the memory controller and validated using the coverage criteria.

-Developed monitor, reference model, BFM, assertions, scoreboard, and checker for testbench implementation.

-Features like register access, chip select, memory timing parameters, suspend and resume features are verified in this project.

R&D Embedded Firmware Intern Company: Titan Company Limited, Chennai Dec 2016 - Jun 2017

-Developed an Ultra-Low power activity tracking wearable using the Bluetooth Low Energy (BLE) microcontroller.

-Used the tools such as Sensor Controller Studio, Code Composer Studio, SmartRF Studio for integrating various sensors with the BLE board.

CERTIFICATION COURSES

VLSI Frontend Design Verification – VLSI Design Flow, System Verilog, UVM, ASIC Verification Concepts, Verification IP Development SOC Verification using System Verilog System Verilog Assertions and Coverage RTL Design using Verilog HDL

Build UVM Testbenches from scratch Design for Test (DFT) Fundamentals Programming in Python

Static Timing Analysis System Verilog Testbench Constructs IC Design Process

HONORS & AWARDS

-Winner in Texas Instruments India Analog Maker Competition held at TCE – Anna University.

-Secured Winning Alliance Award in First Tech Challenge, a robotic event conducted by Caterpillar (India).

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