Raleigh J Boulware

Dacula, GA ***** 770-***-**** adcdyl@r.postjobfree.com

Staff Hardware Design Engineer

Accomplished Senior Electrical Engineer with 23 years of experience in designing, developing, testing and bringing new products to market. Dives into hardware, firmware and system level design issues to manage projects from conception to completion. Offers diverse technical background and strong communication skills.

Core Competencies

Hardware Design

Prototyping

Verilog

FPGA

Analog Design

VHDL

Testing

Strong work ethic

Firmware

Schematic Capture

Troubleshooting

Self-motivated

Leadership

PCB layout

Manufacturing

Cross-functional teamwork

Professional Experience

Technicolor: Staff Electrical Engineer 11/15/2015 – present

Hardware design lead for Cost reduction on multiple high volume prodcuts increasing Gross margins by $5.00 to $9.00.

Lead Hardware design engineer for DOCSIS 3.1 Gateway based on both the Broadcom BCM3390 and Intel Puma 7 SOC with 2.4Ghz and 5Ghz Wifi radios, telephone interface, Ethernet, MoCA and IoT interfaces such as BLE and Zigbee. I have taken these products form concept to mass production. My Responsibilities included:

oCreating hardware design specification documents for our Gateway products.

oChecking and reviewing schematics and board layout files with the various ODMs and technology partners for these products.

oManaging all the Design Verification testing and developed new procedures for testing our products.

oWorking in the lab for prototype bring up and debug using equipment like oscilloscopes and volt ohm meters.

oConducted weekly conference calls with ODMs to address design recommendations and to support DOCSIS UL, FCC WiFi and MOCA certifications.

oReleasing all design documents, test data, schematics and BOM to Agile for mass production.

oWriting ECOs for Agile BOM changes and modifications

Cisco systems, Staff Electrical Engineer: (2007 – 2015)

Lead Engineer for all Intel Puma6 base products, which included the Comcast XB3 Gateway. I managed these products from concept to mass production. These responsibilities included:

oCreating hardware design specification documents for our Puma6 products.

oReviewed schematics and board layout files from the ODM and advised them on changes and updates to improve the design.

oDebugged low level boot up issues involving the PCIe interfaces using oscilloscopes and volt meters.

oTrouble shooting of various types of Memory interfaces on the Puma6, NAND Flash, DDR2 interface.

oWorked with the SVT team on different stability issue with the product.

oWorked with Software team for low level product bring up and debug.

oPerformed compliance testing on the various physical layer IO interfaces like USB, Ethernet on the .

oPerformed Physical and Environmental testing for the customer to prove customer specs.

oPerformed High Voltage Surge testing on all the Interfaces to the Product using Surge test equipment.

oGave corrective action to the ODM based on the Lab and Design Verification test results.

Lead Hardware Design Engineer for High Volume Digital Set-top Boxes. I managed all the board related aspects of the design from concept to mass production. These responsibilities included:

oPerformed schematic capture, and work with the CAD department for board layout.

oTraveled to Juarez Mexico for proto typing and manufacturing of the product.

oPerformed Lab low level bring up and testing for timing and signal integrity.

oUsed various Scopes and logic analyzers from Tektronix and Agilent to do compliance testing on USB, Ethernet, HDMI, SATA

oPerformed trouble shooting for various memory interfaces, Flash, DDR or SRAM.

oMeasured timing between various voltage rails for proper voltage rail sequence bring up.

oPerformed stability testing of the product over different extreme temperatures in thermal chamber.

oPerformed thermal management testing at high temperatures to assure sufficient thermal margin on each component.

oReleased design files, test data, and BOM to production in Agile.

Scientific Atlanta, Senior Electrical Engineer: (1996 – 2007)

FPGA Engineer for the second-generation QPSK Demodulator

oCreated documents and functional block diagrams for the state machine to process MPEG packets on a real time basis.

oWrote FPGA code using Verilog for the MPEG state machine.

oSynthesized the code using the Xilinx software tool set.

oUsed Model Sim to simulate the MPEG state machine.

oUsed a logic analyzer to debug various states of the state machine in real time.

oReleased the code for manufacturing after development.

Hardware Engineer for the second-generation Explorer set-top box, my responsibilities included:

oResponsible for all the digital hardware for the project.

oPerformed trouble shooting for various memory interfaces, Flash DDR or SRAM.

oTraveled to Juarez Mexico to support manufacturing build.

oMeasured timing between various voltage rails for proper voltage rail sequence bring up.

oPerformed stability testing of the product over different extreme temperatures in thermal chamber.

oPerformed thermal management testing at high temperature to make sure of sufficient thermal margin in each component.

Engineering skills and abilities

High speed SERDES board level design SDRAM, DDR, DDR2, USB 2.0, PCIe, Gigabit Ethernet, HDMI

Have a working knowledge of the Intel X86 processors and Atom X86 processors

Have working experience with Older Pentium PCI type mother boards and architecture

Knowledge of high volume automated test fixtures and test stations.

VHDL and Verilog RTL design for FPGAs

Very Knowledgeable with High speed scopes Agilent and Tektronix for high speed Debug and Compliance testing.

X86 CPU local busses interface logic using CPLDs and FPGAs

DRAM memory interfaces using FPGAs

Ethernet Chipsets SMSC, Marvel.

Surface mount and through hole soldering with soldering iron and hot air.

Board design tools and packages:

Allegro Schematic Capture Cadence PCB layout tools.

Mentor Graphics schematic capture package (Design Architect).

Mentor Graphics Expedition Schematic and board layout software.

Pads Perform logic capture and board layout.

OrCAD Schematic Capture Cadence PCB layout tools

Programing experience:

Intel X86 Assembly language

C:

Education

Georgia Institute of Technology, Atlanta, Ga.

Bachelor of Electrical Engineering graduation date June 1996

Football scholarship

Contact this candidate