Design Engineer Power
Resume:
Hiral Gohil
Physical Design Engineer
* ****** ** ******** ** Physical Design Engineer
***********@*****.***
Career Objectives:
I’m seeking a position in an organization to utilize my skills, abilities and enhance my knowledge in physical designing that offers professional growth, while being resourceful, innovative and flexible. Experience:
Frenus tech Pvt Ltd Bangalore,Karnataka
July 2018 -september 2019
● Execution of Netlist-to-GDSII (cadence tool)
● Generation of SDC and Netlist through logical synthesis
● Implemented functional and timing ECOs
● Generation of clock tree synthesis
● Fixing timing violation(setup and hold) along with that fixing design rule violation(max-transition, max fan- out, max capacitance)
● Knowledge with chip level floor-planning, pin planning, clock tree synthesis, Placement, optimization Routing, Parasitic Extraction, Static Timing, IR drop analysis, Physical Verification and sign off Clock design, Optimization, Timing Analysis, DRC/LVS, LEC and sign off
● Analog layout of logical gates in virtuoso ( cadance ) Relcon system Vadodara, Gujarat
Sept 2017- feb 2018
Hardware testing, Troubleshooting and Quality control
Tested the functions for enable/disable pump lock, preset, and interlocks alarms, etc.
Report Application with support various functionality like auto generation of TT receipt, report
validation, trends, configuration, maintenance, price change.
Assembled electronics equipment, test and troubleshoot the issues. Skills:
EDA Tools Cadance
Logical Synthesis Genus
STA Innovus
Operating Systems Windows, Linux
Scripting Language TCL, shell
Physical Verification PVS
Analog layout Virtuoso
Education:
Sr No Name of Examination Board Year of Passing Percentage 1 B.E (IC) G.T.U June – 2017 6.84 CGPA
2 H.S.C G.H.S.E.B March – 2013 50
3 S.S.C G.S.E.B March – 2010 89.73
Projects:
Project 1: SHA-256 Cryptographic hash Algorithm block Gate count : 14000
Frequency : 250MHz.
Tool used : Cadence
Technology : 45nm (TSMC)
Metal layer : 6
No of clock : 1
Objective : To do synthesis, floor planning, power planning, placement, CTS, routing, Design Signoff, generating GDS II
Responsibilities:
Done the Power planning to meet IR drop across the core by increasing the number of
stripes and increasing the width of the metal layer
Performed Netlist need to be Re-Synthesized and make LEC pass
blockages Placement congestion was reduced by cell padding, placement
constraints Worked on Timing
margins Fixing of timing violations – Setup and Hold by keenly analyzing the report and
Fixing of DRC Violation
Personal Detail
Gender : Female
Date of Birth : 09 January, 1996
Marital Status : Single
Language : English, Hindi, Gujarati
Place of Birth : Vadodara - Gujarat
Key Strength : Confident, Honest, Take Initiatives, Starving to learn new things
Declaration:
I hereby declare that the above written particulars are true to the best of knowledge and belief. Place: Gujarat ( Hiral gohil)
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