SHARATH CHANDRA CHALLA

Long Beach, CA *****

858-***-**** adc9ta@r.postjobfree.com www.linkedin.com/in/sharathchandrachalla/

SUMMARY

•Electrical Engineering graduate with VLSI and Mixed signal IC design emphasis.

•6+ months of training experience in IC Physical Design and has in-depth knowledge of industry standard tools like Synopsys ICC, Cadence, Virtuoso, Simulink, Design Compiler.

•Experience with Formal verification and Physical verification using LEC, DRC/LVS.

•Proficiency in Floor planning, Place & Route, Clock tree synthesis, Static timing analysis, Signal integrity, Timing Engineering change order techniques and Tradeoff techniques.

•Looking for full time opportunities in IC Physical design, ASIC Design, SoC Design and Digital design.

EDUCATION

Master of Science in Electrical Engineering

California State University - Long Beach Jan 2018 - May 2020

Bachelor of Technology in Electronics and Communications Engineering

Jawaharlal Nehru Technological University, Hyderabad Sep 2013 - Jun 2017

TECHNICAL SKILLS

Programming languages: Embedded C, C++, Verilog, VHDL, Python, Perl, TCL, SPICE & Assembly language

Software tools: Synopsis IC compiler, Cadence Virtuoso, Simulink, Xilinx Vivado, Microwind DSCH, MATLAB, HSPICE, PSPICE, Design Compiler, Tango, LEC, Calibre, DRC/LVC, Keil software, Arduino, MAGIC, GUNA, ADS

PROFESSIONAL EXPERIENCE

Physical Design Engineer, Institute of Silicon Systems, Hyderabad, India Dec 2016 - Jun 2017 Worked on 14nm server chip design projects (CPX (Cupperlake) and ACF (Ash Creak False)) with Fin Field effect transistor (FinFET) technology which includes multiple sections in chip level design for Intel Corporation.

•Understanding the specifications and features of a circuit cell.

•Performed backend Physical design for block level using Synopsys (ICC) tool including synthesis, placement, CTS & Routing, STA.

•Carried out Multiple corner extraction and STA to verify design.

•Implemented Functional and Timing Engineering change orders (ECO).

•Follow up Formal verification using Logic Equivalence checking (LEC) and Physical verification (DRC/LVS).

•Validated the design using Tango, Duet, Xenon and Aspen.

•Generated GDS-II file for section integration and finally OASIS file is given for the tape in of the chip.

•Worked on block level implementation (Netlist to GDS-II)

ACADAMIC PROJECTS

Design and Layout of a Super sensitive intruder alarm circuit

Designed and implemented a light detecting circuit using IC 555 timer, LM-358 opamp, IR sensor and receiver.

•Design of VHDL Model of smart sensor

Built a VHDL model of smart sensor by implementing algorithm for smart sensor with noise cancellation using IEEE 1451 communication standard.

•Design and Layout of a Portable device for accessing offline storage using Raspberry Pi

Handled the design of a WiFi router which enables offline access to a storage device using Raspberry Pi-3 and Visual kernel, Linux kernel and HTML.

•Design and Layout of a 16-bit Multiplier using Wallace tree algorithm on FPGA kit

Carried out the design of an RTL code of 16-bit Multiplier by using an 8-bit Wallace tree algorithm on Basys-3 FPGA kit using Verilog on Xilinx Vivado tool. Interfaced the push button, LED, 7 Segment display and switches for inputs and reset and achieved 47.6% IO resource utilization post implementation.

•Design and Physical implementation of 8-bit modulo adder

Designed an 8-bit modulo adder with pipeline architecture in 32nm technology. Implemented the design by using three metal layers and adhering to the concept of standard cell in Cadence Virtuoso suite and minimized the Energy delay product to 26.9 pS*pJ and an area of 90.8 um^2.

RELEVANT COURSEWORK

Electronics: VLSI Design (EE535) Mixed signal IC Design (EE534) Microelectronics (EE535A) Adv Microprocessors and embedded control (EE546) Computer Communication Networks (EE545) CMOS Electronics (EE532).

Wireless Communications: Analog/ Digital communication, Spread spectrum communications, High speed communication circuits.

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