Medical Power

DENNIS BECKUS

California Resident

408-***-**** cell: 408-***-**** *******@*****.***

OBJECTIVE

To obtain a position as a Senior Layout Mask Designer

HIGHLIGHTS AND SKILLS

Over 20 years of experience in IC/CMOS/BiCMOS Layout Design

Detailed full chip planning, scheduling and chip leading

Analog, Digital, RF, ESD and Memory Layout experience

Standard Cell Library layout experience

Mentor IC Station and Cadence XL experience

DRC-LVS-ANT verification experience using Assura, Calibre and PVS tools

TSMC(6), IBM (2), JAZZ (2) and UMC(2) process experience

Excellent team player and highly motivated in all related layout assignments

WORK EXPERIENCE AS A “IC LAYOUT MASK DESIGNER”

Nov – 2018 to May – 2020 – Navitas Semiconductor – El Segundo, Ca

Responsible for layout on various Analog blocks : PMU Top, StateMachine,

RefTop, Boot Drivers, esd cells and top level hookup.

Used Cadence VirtuosoXL and Calibre verification. TSMC .18 process.

This was an offsite remote contract.

Feb – 2018 to June – 2018– Ferric Semiconductor – New York City, NY

Responsible for layout for Vref, Refpor, Opamps, LDO Regulators and NVM

circuits. Used Cadence VirtuosoXL and Assura verification. Deep Nwell 28nm

Process. This was an offsite remote contract.

Aug - 2016 to Feb - 2018 // Feb -2014 to Dec - 2015//Dec - 2011 to Nov - 2012 R2 Semiconductor – Sunnyvale, Ca

Responsible for layout on Power Management Circuits. Opamps, Vreg, Clamps, HV Switch Drivers and Charge Pumps The above circuits consisted of using extreme analog techniques (cross coupling – common centroid – current mirror/

cascade matching – adding dummy devices – adding antenna diodes) SoC

Used Cadence Virtuoso and Assura. Deep Nwell .18-28nm- 40nm-90nm process. The above layouts were for integration into a System on Chip (SoC).

July - 2018 to Nov – 2018 // Dec – 2015 to June -2016– Cirque Corp – Salt Lake, Utah

Responsible for layout for ADC_Gref, ADC_Dac, ADC_Ref_Amp and BiCmos circuits. Used Cadence Virtuoso and Assura verification. TSMC Deep Nwell .18

Process.

July- 2013 to Feb - 2014 - Echelon Corporation - San Jose, Ca

Responsible for layout of IO Pads and ESD structures. Modified many existing

analog layouts per engineering requests for better performance for the ADC block. Also responsible for adding in many level shifters and DCAPs to the

existing chip area. Used Cadence Virtuoso XL and Calibre verification.

SMIC .18 Process.

Nov – 2012 to July – 2013 – Qualcomm (Summit Micro) – Draper, Utah

Responsible for layout of bandgaps, delays, drivers, comparators, power supply’s and LDO V/R with emphasis on matching, cross coupling, shielding and isolation. Used Cadence Virtuoso and Calibre verification. TSMC .18 Process.

Sept - 2010 to Nov - 2011 - Proteus Bio Medical – Redwood City, Ca

Responsible for planning and layout for a Medical Sensing ADC chip. This included layout for Bandgap, Power Supplies, OSC, Vreg, IO Pads and top

level chip hookup. Also Responsible for layout on 2V, 3V and 5V standard cell libraries. Used Cadence XL, Fujitsu .18 Process, Calibre and Assura verification tools.

Sept – 2009 to Aug – 2010 - InVisage Technologies - Menlo Park, Ca

Responsible for layout on a Pixel ADC circuit. This included Digital Layout for

row and column cells for the Pixel Array using 1.2u pitch, 7 stages of timing

and comparator cells. Analog Layout for 7 stages of OPAMPS and MDAC’s.

Used Cadence Virtuoso, Assura and TSMC .11 process.

2000 to 2009 - Maxim Integrated Products (SP and C Group)

From 2000 to 2009 I worked with the Signal Processing and Conversion Group for approximately 6 months of each year.

I was responsible for planning, scheduling, leading, top level hookup and working with other lead designers on many Analog circuits.

This included Standard Cell libraries, Digital, Analog Cmos, BiCmos and

I/O ESD pad cells.

2000 to 2009 - Foveon Inc - Santa Clara, Ca

From 2000 to 2009 I worked with Foveon for approximately 6 months of each year. I was responsible for layout on many Image Sensor Circuits. The majority

of layout was Digital. This included column, row cells for Pixel arrays and a

number of control logic cells. The Analog layout included Amplifiers, Bias and A to D converters. Used L-EDIT, Mentor and TSMC .18 process. This project was for DSLR Camera’s.

BUSINESS REFERENCES

Mr. Dave Maes 408-***-**** ( Maxim Integrated Products)

Mr. Tom White 408-***-**** (R2 Semiconductor)

Mr. Larry Burns 650-***-**** (R2 Semiconductor)

Mr Mauro Sirini 408-***-**** (Maxim Integrated Products)

Mr. Milton Dong 510-***-**** (InVisage and Foveon)

Mr. Danny Barlow 480-***-**** (Qualcomm)

Mr. Jeff Berkman 408-***-**** (Proteus Bio Medical and Echelon Corporation)

Mr. Brent Quist 801-***-**** (Cirque Corp)

Mr. David Jew 917-***-**** (Ferric Semiconductor)

Mr. Marco Giandalia – 310-***-**** (Navitas Semiconductor)

Mr. Yusuf Haque – 650-***-**** (Maxim Integrated Products)

COMPANY REFERENCES

(consulted with the following companies from 2000 to 2020)

Advanced Micro Devices Microchip Technology

American Micro Systems (ON Semi) Micosoft

Bitwave Semiconductor National Semiconductor (TI)

Cirque Corp Navitas Semiconductor

Echelon Corporation Proteus Bio Medical

Ferric Semiconductor Qualcomm

Foveon Inc. R2 Semiconductor

L3Harris Si Time Semiconductor

Hewlett Packard Slicex

Intel Corp. Toshiba

InVisage Technologies Western Digital

Lockheed Martin Corp Renesas Electronics (Intersil)

Maxim Integrated Products

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