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System Engineer, C++, Python, Matlab, Fpga, Rtl, Cuda, Verilog, Hls

Location:
Cleveland, OH
Posted:
May 14, 2020

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Resume:

JAI RAJGARHIA

**** * **** ****** *** ***, Cleveland, OH 44113

412-***-**** adc7mj@r.postjobfree.com

EDUCATION

Carnegie Mellon University Pittsburgh, PA

M.S. Electrical and Computer Engineering Aug 2017 - May 2018 Carnegie Mellon University Pittsburgh, PA

B.S. Electrical and Computer Engineering Aug 2013 - May 2017 WORK EXPERIENCE

Viasat Inc. Cleveland, OH

System Engineer July 2018 - Present

Designed a communication system that implemented Digital Signal Processing (DSP) algorithms in C++

Accelerated the algorithms on GPUs using CUDA bringing real-time delay of the system to under 1 ms

Tested the algorithms for correctness using MATLAB simulations which were automated using Python scripts, creating a gold standard for reference

Fine tuned DSP algorithms on FPGAs using SystemVerilog for Forward Error Correction (FEC) analysis improving

exibility and overall capabilities of the design, which led to more precise computations Carnegie Mellon University Pittsburgh, PA

Graduate Teaching Assistant Jan 2018 - May 2018

Teaching assistant for the undergraduate Digital Signal Processing course at Carnegie Mellon

Organized o ce hours, graded homework assignments and exams, and explained key concepts to students Zimperium Dallas, TX

Software Developer Intern May 2016 - Aug 2016

Implemented and integrated a mobile device management(MDM) system into the company’s facade server

Implemented server classes and methods to handle incoming client requests to the facade server

Code successfully pushed into production

SKILLS AND TECHNOLOGIES

Languages & Skills C++, CUDA, Python, SystemVerilog, MATLAB, Stochastic Processes, gRPC Technologies Simulink, Altera toolkit, FPGAs, GPUs PROJECTS

Adaptive Noise Canceler Pittsburgh, PA

Individual Fall 2017

Implemented an adaptive noise canceler using Widrow’s Least Mean Square Algorithm(LMS) and the Recursive Least Squares(RLS) algorithm

System consisted of a simple primary and reference channel with the implementation focusing on noise removal from the primary channel

Physics Simulator Pittsburgh, PA

Team of 2 Fall 2016

Implemented a 2D visual simulator of objects in free fall in System Verilog using a Nexys 4 FPGA

Design consisted of a maximum of 16 bodies behaving as per Newton’s law of gravitation

Implemented xed point ALU to ensure precise math MIPS Architectural Simulator Pittsburgh, PA

Team of 3 Spring 2016

Designed a simulator in System Verilog to execute MIPS instructions

Superscaled to support two concurrent processors with stalling and forwarding



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