Lead SW Architect
Resume:
SATENDAR SINGH (Lead SW Architect)
Stockholm, Sweden +46-706******
Skype: satendar23 **********@*****.***
CAREER SUMMARY
System Architect with around 15 years of R&D experience in the PHY / MAC Layer of Wireless Communication Systems (5G NR, LTE, Wi-Fi) and in Mobile Audio domain
Actively involved in the entire life cycle of embedded product development with technical expertise in DSP firmware and embedded software
Possess around 5 years of project management and team leadership experience PROFESSIONAL EXPERIENCE SUMMARY
Company Location Position Duration
Tieto Corporation Stockholm, Sweden Lead SW Architect 4 months Jan 2020 – Present
Arctos Labs (Huawei) Stockholm, Sweden System Architect 2 years Jan 2018 – Dec 2019
Cybercom (Ericsson) Stockholm, Sweden
Senior Technical
Consultant
5 months
Aug 2017 – Dec 2017
Cavium Inc. Bangalore, India Lead DSP Engineer
1.3 years
May 2016 – Jul 2017
Samsung Electronics
Suwon (HQ),
South Korea
Senior R&D Engineer /
Technical Manager
5.2 years
Feb 2011 – Mar 2016
MindTree Ltd Pune, India Technical Lead
8 months
May 2010 – Jan 2011
Nvidia Corporation Pune, India
System Software
Engineer
4.8 years
Sep 2005 – Apr 2010
EDUCATION
Indian Institute of Technology (IIT) Guwahati, India Master of Technology Aug 2003 – Jul 2005
Specialization: Signal Processing
TECHNICAL SKILLS
High Level Languages C, C++, MATLAB, CUDA-C, Python Assembly Languages / Intrinsics ARM7-TDMIS, Tensilica ConnX BBE16, Tensilica Hi-Fi 2 Audio Engine, Samsung SRP3R
HW Description Language Verilog, VHDL
Operating Systems Linux, Windows CE 6, Windows Mobile 6.5, Android 2.2 Development Methodologies Agile (Scrum), DevOps
Version Control Systems Perforce, SVN, Mercurial, Git Development Tools Xtensa Xplorer, MS Visual Studio, Matlab Simulator, RealView ICE, Code Composer, Eclipse, ModelSim, Vivado, Quartus
TECHNOLOGIES
DSP Architectures Tensilica ConnX & HiFi 2 Audio DSP, TI C66x RISC Architectures ARMv4, ARMv7, PowerPC e500
FPGA Architectures Xilinx ZU21 RFSoC, Intel Arria10 Network Standards 5G NR, LTE, LTE-A, WLAN IEEE 802.11n Broadcast Standards DVB-T2, DVB-S2, ATSC 3.0
Audio/Speech Standards Mp3, EAAC+, Ogg-Vorbis, AMR-NB, AMR-WB Page 2 of 2
KEY PROJECTS AND ACCOMPLISHMENTS
Tieto Corporation Stockholm, Sweden
Lead SW Architect Jan 2020 – Present
Performance analysis of Xilinx ZU21 FPGA and Intel PAC N3000 FPGA solutions of 5G NR LDPC codec and its compatibility with Intel FlexRAN v20.02 reference architecture Arctos Labs AB Stockholm, Sweden
System Architect Jan 2018 – Dec 2019
Analysis of 5G / LTE localization techniques and design of mobility profiling concept to enable dynamic traffic steering and efficient Radio Resource Management for 5G C-RAN system.
Feasibility analysis of CUDA Implementation of 5G NR MAC scheduler algorithm on Nvidia Tesla GPU Architecture using data parallelism techniques
Analysis of cache management techniques and design of memory architecture to resolve cache memory bottleneck issues for 5G NR layer-2 work-loads Cavium Networks Pvt Ltd Bangalore, India
Lead DSP Engineer May 2016 – Jul 2017
Design and implementation of DSP driver and FAPI DL PDU parser for PHY DL channels of LTE Small Cell and DL functional verification on Cavium’s Octeon Fusion-M FPGA board. Samsung Electronics Co., Ltd Suwon, South Korea
Senior R&D Engineer Feb 2011 – Mar 2016
Achieved 10% performance improvement on the execution speed of MAC and MAC-PHY interface (FAPI) of the Small-Cell LTE eNodeB SoC on PowerPC processor
Supervised Bullseye code coverage (Google test) projects for 3 customer releases of LTE L2-L3 SW achieving 100% functional and conditional coverage within the stipulated 3 months
Simulation and DSP implementation of Uplink LTE Co-ordinated Multi-Point (CoMP) using Joint Reception and Processing scheme for Macro eNB system
Steered WLAN (IEEE 802.11n) transceiver link-level simulator development and performed feasibility study of PHY implementation of future WLAN (IEEE 802.11ac) system on Samsung SRP3R DSP
Implemented LDPC decoder using TDMP algorithm and improved overall performance of the DVB-T2 receiver system by 6 dB by fine tuning the parameters of LDPC decoder MindTree Ltd Pune, India
Technical Lead May 2010 – Jan 2011
Designed poly-phase filter structure for the frequency interpolation module to improve the performance of the DVB-T2 Receiver System by 20 MIPS on Tensilica ConnX BBE16 processor Nvidia Graphics Pvt. Ltd. Pune, India
System Software Engineer Sep 2005 – Apr 2010
Devised low-power silence detection and removal algorithm to support gapless playback of MP3, AAC and WMA streams using DirectShow framework such that the time gap between 2 audio tracks remains less than 5 ms
System integration of speech codecs AMR-NB and AMR-WB using ALSA drivers and APIs to facilitate audio playback and recording functionalities through I2S and PCM audio interface.
Executed performance optimization of AMR-NB decoder using ARM7TDMI-S instructions to achieve performance figure of 18 MIPS on ARMv4 processor
Performed execution speed optimization of EAAC+ decoder using Tensilica’s core assembly instructions and Xtensa HiFi-2 Audio Engine instructions to secure performance figure of 40 MIPS GLOBAL EXPERIENCE
Around 3 years of working experience in Sweden (since Aug 2017)
Over 5 years of work experience in South Korea (Feb 2011 – Mar 2016)
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