Electrical Engineering Design

MACAN TADAYON U.S CITIZEN GPA: *.*

Email: *******@*****.*** Phone: 818-***-**** Linkedin:www.linkedin.com/pub/macan-tadayon/84/405/44b/

EXECUTIVE SUMMARY

Seeking a full time or part time position in the Electrical Engineering field. Passionate about learning and helping others.

Certifications: CompTIA. Network +: Certified. Network Introduction: Certified, Network Basics: Certified.

Software Skills: Proficient in EDA CAD Tools: Cadence Virtuoso, ADS, PSpice, LT Spice, MATLAB, Lab View, Python, C, C++, Assembly, Perl, Verilog, Microsoft Office, Excel, Power Point, Word.

Hardware Skills: Experienced in using Electrical Lab Equipment (Network Analyzer, Oscilloscopes, DMM, VNA, etc.)

EDUCATION

UCSB, Ph.D Electrical Engineering GPA= 4.0 Jan 2019-Jun 2022

UCLA, M.S Electrical Engineering GPA=3.70 Sep 2015-Dec 2016

UCLA, B.S. Electrical Engineering Major GPA= 3.78 Sep 2012-June 2015

Relevant Coursework: Analog/Digital Design RF Circuit Design Microwave Circuit Digital Signal Processing Systems and Signals Power Electronics Feedback Control Device Physics Numerical Analysis Digital Logic Design.

WORK EXPERIENCE:

SeeDevice Inc. Buena Park(CA) Aug 2019-Present

Senior Analog Mixed Signal Designer

Taped- out a 64*64 array of Rolling Shutter Image Sensor in 130nm TSMC with frame rate of 10Kfps.

Taped out a high-speed LIDAR system using direct time of flight with 1ns pulse and less than 1ns TDC resolution in 130nm TSMC.

Designed a 4-phased high-speed indirect-time of flight pixel with modulation frequency of 75MHz in 65nm TSMC.

Designed the state-of-the-art finger on display (FOD) sensor pixel capable of capturing high quality image & edge detection.

Designed a bias generator using bandgap and precise current splitter.

Designed a self-biased low jitter DLL(PLL) for the 12-bit hybrid TDC with 1ns resolution for long range LIDAR applications.

Lockheed Martin Goleta(CA) Dec 2017-Aug 2019

Analog IC Designer (RF/Mixed Signal)

Optimized the design of 3GHz ring oscillator for image sensor/TOF application.

Design of 12-bits single slope column-parallel ADC for image sensor application.

Design of current-steering as well as R-2R DAC for building image sensor peripheral blocks.

Designed a low noise low power CTIA for analog front end in SWIR application.

Worked on technologies such as CMOS 180 nm, 90 nm, 45 nm for developing the next generation of ROICs.

Broadcom Irvine(CA) Sep 2017-Dec 2017

RFIC Design intern

Optimized and verified highly integrated transceivers designed for Bluetooth/FM/GPS applications.

Performed data and failure analysis, debugging and resolve RF system malfunctions and issues.

Measured and optimized various design parameters such as phase noise, gain, spurs, noise figure and AGC.

Worked on optimizing the design of LC based oscillator PLL for Bluetooth applications.

Designed an inductively degenerated common source cascode low noise amplifier using Cadence Virtuoso.

Designed using 90nm CMOS technology operating in LTE band 1 (2.11GHz - 2.17GHz).

Met specifications for total transconductance gain of 50mS, 3dB bandwidth of 200 MHz, noise figure of 1.5 dB, IIP3 of -2dBm, and input return loss of -10dB.

Qualcomm

High Speed Mixed Signal Design Intern Raleigh (NC) Jun 2017-Sep 2017

Worked on design and optimizing the PLL for generating the clock of 16 GHz using TSMC 7-nm finFET.

Worked on design and optimizing the auxiliary divider for synthesizer and clock tree.

AEi Systems Los Angeles Jan 2017-Jun 2017

Analog and Digital Circuit Analysis Engineer

Worst-Case Circuit Analysis on Analog, Digital, Linear, RF Circuits using PSpice ORCAD.

Signal/Power Integrity Analysis.

Maxim Integrated

Analog IC Design Intern San Jose(CA) Jun 2016-Sep 2016

A High-Sensitivity and Low-Walk Error LIDAR Receiver

Modified the delay measurement system to achieve the highest performance in terms of gain and walk-error.

Implemented voltage clamps in different part of system to ensure the system to stay in active mode.

Calculated the noise and SNR of the system along with simulating for corner and Monte Carlo analysis to account for the worst case PVT variation in the system using Cadance Virtuoso.

ENGINEERING PROJECTS

Ring Oscillator UCLA April 2015-Jun2015

•Designed a 2.3 GHz common-gate fixed frequency oscillator based on an GaAs E-mode pHEMT for implementing Wifi 11b/g applications.

•Developed a ring oscillator based on Avago ATF-55143 low noise enhancement mode pseudomorphic GaAs HEMT in a 4-lead SOT-343 plastic package.

•Collaborated with a team of two to design, simulate, layout, fabricate, assemble, and test Ring Oscillator using ADS and electromagnetic packages such as HFSS, Sonnet and Momentum.

Schottky Diode Microstrip Mixer (Ratrace) UCLA April 2015-Jun2015

•Designed a 2.4GHz single balanced rat race diode mixer based on GaAs Schottky diode for implementing Wifi 11b/g applications.

•Developed a Ratrace based on Avago HSMS-28ox surface mount RF Schottky barrier diode in a 3 lead SOT-23.

•Collaborated with a team of two to design, simulate, layout, fabricate, assemble, and test Ratrace using ADS and electromagnetic packages such as HFSS, Sonnet and Momentum.

Low Noise Power Amplifier UCLA April 2015-Jun2015

•Designed a 2.4-2.5GHz low noise amplifier based on an advanced e-mode GaAs pHEMT device for implementing Wifi 11b/g applications.

•Developed a LNA based on Avago ATF-55143 low noise enhancement mode pseudomorphic GaAs HEMT in a 4-lead SOT-343 plastic package.

•Collaborated with a team of two to design, simulate, layout, fabricate, assemble, and test LNA using ADS and electromagnetic packages such as HFSS, Sonnet and Momentum.

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