Sign in

Design Engineer Engineering

Chandler, AZ
February 22, 2020

Contact this candidate




**** ******** **** *******: +1-408-***-****

Austin, TX 78749

To use my skills to the full potential with utmost quality assurance and to align myself with the professional growth and goals of the organization with which I seek a long-term career and relationship. CORE COMPETENCIES

Overall experience of 12+ years in VLSI Physical Design while delivering more than 15 taped out projects ranging from TSMC 7nm, 14nm GF, 16ff, 28nm technology nodes.

Very good experience in Synthesis, P&R, ECO modes and Physical Verification on latest technologies for block level and subsystem level P&R closure.

Expertise in resolving various Block level issues includes synthesis, Floor planning, Placement, Clock Tree Synthesis (CTS), Routing, Extraction, ECO, Timing closure, IR drop and Physical verification.

Good understanding of low power design.

Hands on experience in handling different EDA tools – ICC/ICC2, SOC Encounter, Primetime, Design Compiler, Caliber, Star RC-XT.

Good experience in scripting languages PERL, TCL.

Expertise in guiding the teams in resolving various place and route issues, includes checklists, flow issues and place and route issues at different stages of design.

Ability to work independently as well as part of a team.

Very Good experience in interacting with the teams in different locations. EXPERIENCE PROFILE

Working as a Senior Technical Lead Physical Design Engineer for Aricent NA Inc., USA from AUG 2016 to till date

Working as a Lead Engineer in Intel, AUSTIN since 2018 sep

Worked as a Lead engineer in AMD since aug 2016 to aug 2018

Worked as a Technical Lead Physical Design Engineer for Aricent, Bangalore, India from DEC 2012 to JUL 2016

Worked as a Senior Physical Design Engineer for AMD, Hyderabad from JAN 2011 to NOV 2012.

Worked as a Physical Design Engineer for ARM Technologies Pvt Ltd, Bangalore from JAN 2007 to DEC 2010. EDUCATIONAL PROFILE

Post-Graduation: M.S. in VLSI design from Manipal University, Manipal. Graduation:

Bachelor of Engineering (B.E) in Electronics and Communications Engineering from Maduari kamaraj univerisy, Maduari.


Organization: Intel (From Aricent NA INC) from Sep 2018 to till date As part of physical design team involved in below activities.

Working on 10nm project with a frequency of 1.2 GHZ.

Working on subsystem level PnR from synthesis, partitioning, pin placement, floorplanning, placement, routing, CTS, working on ecos with timing closure and Physical verification closure.

Working on the tools ICC2, DC, PTSI, StarRC, Formality and Calibre

Working on Clock and IO constraint generation for TOP and block level

Interacting with the team & Client regularly and resolving various PnR issues.

Worked on timing closure of blocks on multiple modes and multiple corners Organization: AMD (From Aricent NA INC) from Aug 2016 to Aug 2018 As part of physical design implementation team involved in below list of activities

Worked on 7nm TSMC GPU project on block level with a frequency of 2GHZ.

Worked on block level PnR and leading a team of 7 members with 11 blocks. Responsible for P& R, Ecos with timing closure

& PV deliver, resolving various PnR issues and helping the team to fill the checklists at different stages of design.

5 out of 11 Blocks are reusable in top level are instantiated 40 times and took many iterations to converge as area sensitive designs.

Pre routing and pre placing cells to meet the design needs of hbm phy interactions.

Blocks are in complex with feedthroughs, congestion issues, timing closure, drc fixes, IR and sigem fixes.

Worked on the tools ICC2, DC, PTSI, StarRC, Formality and Calibre

Interacting with the team & Client regularly and resolving various PnR issues.

Worked on IP project, helped the blocks from synthesis, Place & Route closure, timing & PV closure. Organization: SmartPlay - ODC, from SEP 2014 to JUL 2016 As part of physical design implementation team involved in below list of activities

Lead for AMD-ODC GPU project with 19 Blocks, Technical Lead and responsible to PnR closure for all the Blocks.

Handled two blocks from Floorplan to GDS deliver.

Handled training sessions for the team to understand the AMD’s TileBuilder flow.

Checklist preparation & Helping the team to understand and complete the targets.

Helped the team to analyze and resolve various flow, congestion, timing, ECOs and PV closure.

Handled multiple blocks with more than 1 million instance size in each ASIC for P&R from Netlist to Sign-off. Organization: STMicro, Noida (As a consultant from Smartplay), from MAR 2014 to AUG 2014

Involved in two taped out projects.

PnR of core blocks for wireless and ING group, resolving all PnR issues. Design sizes range from 3.6M+ to min of 1M instance count with multiple clocks from 950MHz

Work involves floorplan, P&R, CTS, timing ECO generation and eco implementation, fixing DRC & LVS, formal verification, crosstalk and noise analysis, extraction and timing closure

Tools used ICC, PTSI, StarRC, Conformal LEC, and Calibre

Guided a team of 4 working from ODC for same projects Organization: Smartplay-ODC, Bangalore from MAR 2013 to MAR 2014

Block level P&R implementation for the blocks in 28nm technology.

Design is congestion and timing critical with low power design.

RTL to GDS implementation of block with 98 macros, with clock frequency of 250MHz, Total 1.08M+ instance count.

Tools used ICC, PTSI, StarRC, IC Validator, Conformal LEC Organization: AMD, Hyderabad from JAN 2011 to NOV 2012

Blocks are in complex having timing critical with 940MHZ.

Worked on interface timing closure &block level pnr issues.

Worked for Eco projects to clean up the timing issues.

Mentored team members on place and route issues and project deliverables.

Worked on Feedthrus.

Organization: ARM Embedded technologies pvt Ltd, Bangalore from JAN 2007 to DEC 2010

Delivered more than 15 testchips taped out projects with technology nodes from 28nm to 130nm

Worked on multiple test chips for multiple FABS

Handled Blocks in different stages of design from Netlist to GDS.

Pre and post silicon validation for testchips to make sure ARM IP’s are operating at designed specifications

Contact this candidate