Seeking Full-time/intern opportunities that will utilize my skills, knowledge and provide a rewarding career in ASIC/FPGA domain.
SAN JOSE STATE UNIVERSITY FALL 2018
MS in Electrical Engineering (VLSI).
Course work: SOC Design ASIC CMOS design Advanced computer architecture Advanced Digital System design and synthesis System Verilog verification VLSI digital design using Verilog IC design process Hardware modeling using Verilog System Verilog Assertions and Functional coverage STA.
SRI VENKATESWARA COLLEGE OF ENGINEERING, TAMIL NADU, INDIA AUGUST 2014 – MAY 2018
Bachelor of Engineering in Electronics & communications Engineering.
Course Work: RF Microelectronics Electrical engineering and instrumentation Linear Integrated circuits Advanced Microprocessor and Microcontroller Advanced Computer Architecture VLSI design.
EDA TOOLS: Quartus Prime, Synopsys VCS, Synopsys design compiler, Mentor Graphics Model Sim, Xilinx ISE OS: Windows, Linux Mint BUS PROTOCOLS: APB, AHB, I2C, PCI PROGRAMMING LANGUAGES: C, C++, MATLAB, Python. HDL: Verilog, System Verilog, UVM.
SAN JOSE STATE UNIVERSITY SEPTEMBER 2019 - PRESENT
INSTRUCTIONAL STUDENT ASSISTANT - (TUTOR)
Working as an ISA (Tutor) for the course “Digital Design “and conducting lab projects, Assignment on combinational and sequential logic theory and circuits, Verilog modeling of Finite state Machines.
BHARAT ELECTRONICS LIMITED – INPLANT TRAINEE, CHENNAI, INDIA NOVEMBER 2016 – DECEMBER 2016
Worked in the Development and Engineering department that monitors the tank functions.
Involved in testing the tank electronics and optical fire control systems used in the military tanks.
THE DESIGN AND VERIFICATION OF A SYNCHRONOUS FIRST-IN FIRST-OUT (FIFO) MODULE FALL 2019
USING SYSTEM VERILOG BASED UNIVERSAL VERIFICATION METHODOLOGY (UVM).
Designing a synchronous FIFO using Verilog and verifying using UVM test bench environment that can communicate with each port that verifies the correct functionality of data write and data read at the expected time.
BIT MOVEMENT BLOCK ON AHB BUS PROTOCOL USING SYSTEM VERILOG FALL 2019
Designed a bit movement block that works with 32 bits read and write interface that can move data at any bit location on AHB bus as master and slave.
BIT ACCURATE MODEL OF HALF PRECISION FLOATING POINT MUTIPLIER AND ADDER USING VERILOG FALL 2019
Designed and implemented a bit accurate model that takes 12 element input and provides the output using three stages pipelined for multiplier and adder using Verilog.
ROUND ROBIN ARBITER USING VERILOG FSM CODING WITH VARIABLE SLICE PERIOD SPRING 2019
Designed and implemented a Round-robin algorithm that handles 4 request and 4 grant signals in circular order without priority with time slices assigned to each process in equal portions.
A SIMPLE SPREAD SPECTRUM CORRELATOR USING VERILOG AT 333 MHZ SPRING 2019
Designed and implemented correlator that runs at 333 MHz, which can accept base band sample Clock and produce a correlation output using gold code and phase shift keying.
FLOATING POINT ADDER [HALF PRECISION] USING VERILOG IN IEEE 754 SPRING 2019
Designed and implemented a half precision floating point adder in IEEE 754 standard using hardware descriptive language Verilog and GTK wave simulator.
DOT PRODUCT BENCHMARK PROGRAM USING FORWARD CHAINING TECHNIQUE SPRING 2019
Implemented MIPS instruction Set architecture that performs the dot product using Verilog and reduced the clock cycles with the forward chaining technique.
TRAFFIC SIGNAL SYSTEM USING QUARTUS PRIME FALL 2018
Designed and implemented the traffic signal system for two intersections considering all the possibilities With Verilog and implemented using FPGA board.