Design Engineering

SUMMARY

ASLESHA KOTHA

*** * ******* ****, *** **3, Tempe AZ, 85281 Mobile: +1-602-***-****

Email: *******@***.*** https://www.linkedin.com/in/aslesha-kotha/ Master’s in Computer Engineering with focus on mixed signal circuits seeking Intern/Full Time opportunities in the field of Digital/ASIC/RTL/Physical/VLSI/SoC/ Hardware Design starting from May 2020. TECHNICAL SKILLS

Programming Languages: C, Python, MATLAB, Perl

Certifications: Computer Architecture & Organization, Learning FPGA Development, Hardware Modeling Using Verilog, IC Design, Python for Everybody, Python Data Structures, Using Python to access Web Data, Using Databases with Python. Hardware Tools: XILINX ISE DESIGN SUITE, CADENCE (Virtuoso), ICV/Calibre run set usage, PSpice, CST, STARRC. Hardware: RTL Design, Verilog, System Verilog, VHDL, Intel Galileo Gen 2, Arduino, QUARK Architecture. EDUCATION

M.S., Computer Engineering Expected - Dec’20

Arizona State University, Tempe, AZ, USA. CGPA- 3.2/4 Relevant Courses: Digital Circuits and Systems, Hardware Acceleration and FPGA Computing, Analog Integrated Circuits, VLSI Design, Python for Rapid Engineering Solutions, Foundations of Algorithms. B.Tech., Electronics & Communication Engineering Aug’14-May’18 Acharya Nagarjuna University, Andhra Pradesh, India. CGPA – 9.05/10 Relevant Courses: Digital Logic Design, Electronic Circuits, VLSI Design, Digital Communication, Analog Communication, Computer Organization.

WORK EXPERIENCE

RESEARCH ASSISTANT: Under Prof. Dr. Alapati Sudhakar Jan’19 – May’19 Acharya Nagarjuna University, Andhra Pradesh, India.

• Designed and developed a linearly polarized micro strip antenna that operates in UWB frequency range whose bandwidth is between 3-11 GHz using CST tool. Substrate used is Taconic RF-30, patch & feed using copper.

• Calculated S-parameters, VSWR ratio. Achieved a gain of 5db at 5.18GHz & final antenna worked at a frequency of 3.6GHz

(Wi-Max).

PROJECTS

FPGA IMPLEMENTATION OF CONVOLUTION NEURAL NETWORK FOR IMAGE/DIGIT RECOGNITION

• Implemented Convolution Neural Network on FPGA by utilizing the Le-Net 5 CNN as the Baseline Architecture to recognize an Image/Digit from a given input image by training the system and testing it for precision.

• Optimized the system by reducing the latency and improving the energy efficiency by making use of the features - Unrolling and Pipelining. Worked on Xilinx ISE, Vivado Design Suite, and Altera family as a part of coursework. DOT PRODUCT AND SQUARE ROOT ENGINE DESIGN Fall 2019

• Designed a 256-bit bit input Square Root Engine and Dot Product using System Verilog that generates a 16-bit fixed point value. Performed complete ASIC Design flow i.e. RTL and Gate level Netlist functionality test using Modelsim.

• Synthesized the design using DC Compiler. Performed APR, Clock Tree Synthesis free of Setup & Hold Violations using Cadence Innovus, Post layout timing analysis and power using primetime. DESIGN OF 16 WORD x 16-BIT REGISTER FILE Fall 2019

• Designed a 4-to-16 decoder using RVT devices that will drive the corresponding word lines of Register File (active high). PEX has been performed & verified the functionality.

• Generated the layout for 16 16 RF array & integrated it together with the decoder. Performed DRC & LVS & verified functionality using post-layout extracted simulation in all corner cases. 16:1 MUX SYNTHESIS, APR & POST APR Fall 2019

• Designed a MUX (16:1) using the System Verilog code & verified the functionality using Modelsim. Synthesized the design using Synopsis Design Compiler and verified the synthesis netlist.

• Performed APR (Automatic Place & Route) using Cadence Innovus version 17.10, generated reports for area and timing. Post- APR - export GDS is done, imported the GDS into Virtuoso layout, and performed DRC/LVS on the final layout of the design. DESIGN OF STANDARD CELLS (4x1_NAND & RF- Bit cell) USING VIRTUOSO (CADENCE) Spring 2019

• Designed a NAND and Register file bit cell schematic, layout, symbol. Checked DRC, LVS and simulated the layout & schematic.

• Verified the functionality of the standard cell in the pre-layout (test bench schematic) and post-layout (PEX netlist) simulations.

INTERNSHIP EXPERIENCE

Telecommunication Intern at BSNL: Nov’17 – Dec’17

• Worked on 2G, 3G, 4G technologies, high speed broadband, modern transmission systems and switching technology in landline phones, digital switching systems. OFC installations & understanding of live systems in lab.

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