MUSTIKOVILA NAGA KAUSHIK

+1-480-***-**** • adbo53@r.postjobfree.com • www.linkedin.com/in/mustikovilanagakaushik SUMMARY

MS Electrical Engineering student with a focus on Digital VLSI design. Interested in a career in VLSI domain, as SoC/ASIC/Physical Design engineer. Seeking Full Time Opportunities. TECHNICAL SKILLS

Programming, HDL and scripting languages: C, Python, System Verilog, Perl, TCL. Tools: Synopsys Design compiler, Synopsys Primetime Mentor, Modelsim, Cadence NCSim Cadence Innovus, Cadence Genus, Cadence Tempus, Cadence Conformal, Cadence Jasper Gold, Cadence Integrated Metrics Center, Redhawk, MATLAB, Cadence Virtuoso, Gem5, Xilinx ISE.

Operating Systems Knowledge: Linux, Windows System. EDUCATION

Master of Science, Electronics and Electrical Engineering 3.87/4.00 Graduating May 2020 Arizona State University, Tempe, Arizona.

Bachelor of Technology, Electronics and Communication Engineering 7.7/10 GPA May 2018 Indian Institute of Information Technology Design and Manufacturing, Jabalpur, India PROFESSIONAL EXPERIENCE

Digital Design Intern, NXP Semiconductors, Chandler, AZ Summer 2019-Fall 2019

• Worked on High Speed Re-driver IC (140nm process) and performed Automatic Placement Routing (APR), and undertook timing closure for static timing analysis.

• Performed LEC and CPF based verification checks on AON block in Authentication IC (40nm process).

• Block verification for Power Management Unit which includes writing Test bench, assertions and tasks including code coverage analysis and functional coverage analysis.

• Generated Dynamic IR drop maps to analyze hotspots in design.

• Gained knowledge on Power Aware Design methodologies and Clock Domain Crossing. Research Intern, Indian Institute of Information Technology Design and Manufacturing Fall 2017-Spring 2018

• Designed a linear-phase finite impulse response (FIR) notch filter using Fractional Derivative constraints on MATLAB.

• Validated this filter on FPGA for filtering of raw EEG signal recorded real time.

• Reduction of Pass band error by 21% was observed and research paper has been published in chapter of Springer 2018.

• Implemented Frontend and Backend ASIC design flow. Synthesized RTL and performed APR. ACADEMIC PROJECTS

RTL to GDSII (ASIC) of Convolution and Average-pooling of CNN using 7nm PDK Spring 2019

• Design and verification of Convolution and max-pooling engine using Verilog, synthesized netlist using DC compiler.

• Performed Automatic Place and Route (APR) using Cadence Innovus, Gate-level static timing analysis using Synopsys Primetime.

• Verification of Post synthesis and Post-APR timing. Design of a 16-word x 16 bit Register file (RF) using 7nm PDK Spring 2019

• Designed schematic and layout of 16 word * 16-bit register file with one read and write port using 7nm PDK.

• Designed standard cells like I/O Pad, Bit cell and Decoders and modularity is implemented by reusing these designs.

• Optimized decoder design and placement to drive the corresponding word lines (active high)

• Verified LVS and DRC using Hercules and used Calibre for Parasitic extraction used in Post-Layout simulation. Implementation of 64 bit RSA Encryption for Restricted System on FPGA Spring 2019

• The design has been described in Symphony Model Compiler and simulated using SHLS tool o Operating clock frequency of 9.9MHz.

o Throughput is improved by 43x than the conventional architecture. o Throughput was achieved with 6x increase in the amount of hardware and efficient utilization of all resources with interleaving.

Characterization of Energy Delay Curve for 64-bit ALU using 28nm PDK Spring 2019

• Prototyped 64-bit ALU using Synphony Model Compiler and verified the functionality using ModelSim.

• Optimized energy-delay curve by tuning size, supply and threshold voltage. Design of 4 to1 Integrate and Fire (IF) Neuron using 32nm PDK Fall 2018

• Designed layout of digital spiking neuron using mirror adders, logic gates and Flip-Flops. o The inverting property of the full adders is used to decrease the number of inverters in the design of 4-bit adder. o Transistors are sized at transistor level and gate level to attain minimized Power, Delay and Area.

• Verified LVS and DRC using cadence virtuoso and Parasitic extraction using StarRC is performed.

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