Geoffrey (Guang Feng Li) adbavr@r.postjobfree.com

Summary of Qualifications

10+ years’ experience in PCB Hardware Design, Validation and Debug (Up to 25GHz)

Strong experience in Network Modules, NIC, Smartphone/Tablet, MB, Power Supply design

Successful experience in Network interfaces (Serdes 25GHz, QSFP-28, CXP, QSFP+, SFP+)

Successful experience in HS interfaces (LPDDR4, DDR4, PCIe, Ethernet, USB, HT3)

Experience in Analog, Electrical, Instrument, Mechanical, Thermal and Power design

Experience in developing test plans (Electrical/Functional), prototypes and test systems

Familiar with ARM, x86, PIC and TI MCU, FPGA, CPLD, SMPS, LDO, PLC applications

Strong background in PCB schematic and layout design, SI/PI/PDN analysis and validation

Strong testing and debugging with Logic Analyzer, Oscilloscope (Timing, Eye, Compliance)

Proven leadership for hardware system design, PCB bring-up, ASIC validation and issue debug

Goal oriented, team player with sense of confidence and can-do spirit

Technical Skills

Language: Python, Assembly, Verilog/VHDL and PSPICE

Operating Systems: Linux, QNX, Windows XP, Win7/8, Unix Systems

Software Tools: Altium (SI/PI/PDNA), DxDesigner, HyperLynx, Lattice Diamond

Hardware Tools: Keysight/Tektronix SERDES, DDR3, LPDDR2 Logic Analyzer (LA), eMMC/uSD LA, PCIe LA, HT LA, SATA LA, Digitizing Signal Analyzer, Multimeter

Work Experience

Lead Hardware Engineer 2014.02 – 2019.12

Netronome Systems Inc. (Pittsburgh, PA)

Lead hardware design of Network Flow Processing Customer Development Platform (including NFP processor, DDR3, DIMM, PCIe Gen3, Serdes 25GHz, USB, SPI/I2C, Power Supplies)

Lead hardware design of DDR3 memory module (Dual Channel Dual Rank 40bit/72bit, DIMM)

Lead hardware design of network cards (PHY modules: QSFP-28, SFP+, RJ45 ports)

Hardware design, analysis, simulation and support of data center servers and network cards

PCB schematic design and layout (Smart NIC, CPU, LP/DDR4, PCIe, CPLD, SMPS, LDO)

PCB board, modules and NFP ASIC bring-up, SI/PI validation, PDN analysis and debugging

Develop CPLD control with Verilog, automated test scripting with Python

Testing and debugging with PCIe Protocol Analyzer, scope (Timing, Eye diagram, Compliance)

Create hardware design specification, test plan (Electrical/Functional) and validation test record

Performed some PCB board re-work including component replacement

Digital Hardware Designer 2010.07 – 2013.12

BlackBerry (RIM: Research In Motion Limited). (Ontario, Canada)

Hardware research, architect, design and validation on Smartphone/Tablet prototypes/products (including processor baseband, LPDDR1/2 DRAM, eMMC and uSD flash interfaces)

Successfully designed consumer electronic prototypes/products (5 smartphones and 2 tablets)

Lead of OMAP4 based memory interface designs (Smartphone/Tablet prototypes/products)

Lead of next generation AP/CP memory interface designs including core PPs validation

Created processor and component validation, design verification record (DVR) documentations

DRAM and MMC detailed design analysis record (DDR) for processor and component

Analyzed processor and memory interface electrical and timing violation

Memory interfaces schematic and PCB layout design review for prototypes and products

Performed power management, thermal analysis and SW framework for memory interfaces

Validated (Signal/Power Integrity) and debug PCB, processor and components issues

Participated in bring-up for prototype including big boards and form factors

Developed test scripts for automatic testing and debugging

Lab equipment including Protocol Analyzer, Logic Analyzer, scope for validation and debug

Provided engineering support and issue debug during product ramp

Systems Design Engineer 2007.03 – 2009.06

AMD (Advanced Micro Devices, Inc.) Chipset Division. (Ontario, Canada)

Designed and verified computer reference Motherboards (including CPU, Chipset, DDR2/3 Memory DIMM, Audio, Graphics, Wireless, Ethernet, USB, SATA, Clock and Power Management)

Successfully designed PC/Server motherboards (3 PC and 1 NB chips)

Executed Server/Desktop and Mobile Chipsets bring-up and design review (Verilog/VHDL)

Performed ASIC feature review, test plan review, tests and validation

Validated (Signal/Power Integrity) for MB PCB, processor and components interfaces

Improved board level and system design by resolving hardware and software problems

Debugged ASIC design issues for HT3 (2.6GHz) and PCIe (5GHz) interfaces

Exceeded project schedule by planning, executing test plan and driving issues to closure

Addressed issues in PC/Server Motherboard Design, PCB Layout, BIOS, Graphics Driver

Led or participated in related teams (HW, SW, BIOS, FAE, Sales) for issue debug

Senior Hardware Engineer, Team Leader 2005.03 – 2007.02

Techno Scientific Inc. (Ontario, Canada)

TSI design and manufacture NDE (Non Destructive Evaluation) products, from transducers and interface modules to automated scanning, visual tracking, inspection and robotic systems.

Defined electrical and system design specifications for Ultrasonic Flaw Detection Systems

Designed Analog and Digital control circuit of ultrasonic transducer transceiver

Designed electrical system with MCU, PLC, Sensors, Motor Control and Power Supplies

Designed the schematic capture and PCB layout of the transceiver and interface control board

Utilized Cadence schematic capture, PSPICE for electronic hardware and PCB layout design

Improved S/N (Signal Noise Ratio) 4 times. Reduced crosstalk (-40dB). Reduced test time to 25%

Developed microcontroller (MCU with Ethernet) firmware with C and assembly code

Worked with vendors and contractors for ensure system integration and PCB board population

Led the hardware team, closely worked with vendors, customers, and contractors

Education and Training

Master’s Degree in Microelectronics and Solid Electronics 2000

Xi’an University of Technology (assessed by University of Toronto CES)

Bachelor’s Degree in Electronics Engineering (Semiconductor) 1989

Xi’an Jiaotong University (assessed by University of Toronto CES)

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