Engineer Project

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REKHA.S

Vengalapuram(Village&Post),

Tirupattur(Tk),

Vellore Dist,

Pin Code: 635653

Mobile : +91-882******* mailto:**************@*****.*** CAREER OBJECTIVE

To apply my thoughts in a creative and challenging environment, where i could successfully deliver solutions, improve my technical and analytical skills and grow with the organization.

EDUCATIONAL QUALIFICATIONS

DISCIPLINE

INSTITUTE

BOARD/

UNIVERSITY

YEAR

PERCENTAGE Be

(E.C.E)

Podhigai College of

Engineering &

Technology

Anna

university

2014-2018

69.5%

HSC

Govt. Hr.sec.

School

Madavalam

State board 2013-2014 69.0%

SSLC

Govt. Hr.sec.

School

Madavalam

State board 2011-2012 77.0%

CORE COMPETENCY

Ø Basic knowledge of ASIC Design Flow.

Ø Experience in writing RTL models in verilog.

Ø Good understanding of object-oriented programming (OOP) concepts. Ø Skilled in HVLs such as system verilog.

Ø Good knowledge of Digital Design concepts and FSM fundamental concepts. Ø Worked on tools like Questasim from Mentor Graphics. Ø Knowledge on AMBA APB protocol.

Ø Basic knowledge of C

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TECHNICAL SKILLS

Ø HDL/HVL skills : Verilog,System Verilog.

Ø Methodologies : UVM (Universal Verification Methodology). Ø Bus protocols : AMBA APB

Ø Simulators : Questasim

Ø Operating Systems : Windows and LINUX.

Ø Knowledge : RTL Coding, FSM based Design, simulation, Code Coverage, Functional Coverage, Synthesis.

VLSI PROJECTS

U ART

Environment: Verilog

EDA Tools: Questasim.

Description:

Ø UART stands for Universal Asynchronous Receiver / Transmitter. UART is a stand- alone IC.

Ø UART is usually an individual IC used for serial over a computer or peripheral device port.

Ø It transmits and receives the data through two wires only. Ø It supports full duplex communication.

Role:

Ø Implemented RTL using Verilog HDL.

Ø Created TB for generating the input stimulus and monitor the output responses. Ø Verified the full duplex communication by driving the traffic from either side of the UART RTL.

Ø Verified the Data path with parity Enable/Disabled, Single and Multiple STOP bits, all character lengths by programming the UART registers through APB bus. Ø Verified UART using APB interface in UVM environment Ø Generated Functional Coverage for the RTL Verification APB Protocol

APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced, low complexity signal list (for example no bursts). Role:

Ø Created Verification plan and Architected the UVM based verification environment Ø Involved in creation of verification plan, coverage plan. Ø Created an APB master Environment including Driver, Monitor, Scoreboard etc., from the scratch

Ø Verified the APB protocol by integrating single master (BFM) and Slave (DUT). Ø Created scenario to verify the functionalities including wait states. Ø Worked on implementing the assertions

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FINALYEAR PROJECT

Project Area : Embedded System

Project Title : “REAL TIME PREDICTIVE ANALYTICS”

Project Role : Team leader

PERSONAL TRAITS

Ø Self confidence

Ø Good in teamwork

Ø Honesty & self-respect

Ø Hard working

PERSONAL PROFILE

Name : Rekha.S

Father’s name : Sankar.R

Date of birth : 05-06-1997

Gender : Female

Nationality : Indian

Religion : Hindu

Marital status : Single

Languages known : Tamil, English, Telugu

DECLARATION

I hereby declare that the above particulars are true and correct to the best of my knowledge.

Place: Yours Sincerely,

Date: (REKHA.S)

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