Engineer Design

Naveen Dutta

Thornton, CO *****

303-***-**** adb45c@r.postjobfree.com www.linkedin.com/in/naveen-dutta

Senior FPGA and ASIC Design / Applications Engineer

FPGA design and applications engineer with extensive experience in telecom and semiconductor industries. Experience with next generation product requirements, specification, testing, documentation and customer support. Expertise includes design/development, verification and debugging of ASICs/FPGAs using VHDL/Verilog, and embedded processors, design of multi-layer complex circuit packs and embedded software development.

Core Competencies

Intimate knowledge and experience with hardware / firmware design process, from requirements through product release of product development stages.

High-speed digital circuit design Complex state machine design.

Ability to write highly portable, parameterizable, modular and scalable code in VHDL and Verilog to allow portability, reusability and maintenance.

Proficient in Simulation, Synthesis and Timing Analysis of complex designs.

Programming and scripting skills Reverse engineering.

Project Management and Scheduling.

Excellent presentation skills.

Ability to juggle many tasks while remaining calm and focused.

Interviewing / recruiting / teaching-mentoring.

Professional Experience

Xilinx Longmont, CO 06/2012 – 02/2020

Senior Applications Engineer

Product Requirement Team (PRT) Lead for Vivado IP Integrator, Hardware Software Integration, Memory Initialization, Board / IP automation and Debug flows.

Managed PRTs, helped write specifications, user interaction scenarios, tracked milestones of development, demoed feature to various stake holders, and reported on quality / ease-of-use of feature.

Prioritized and championed high-value customer-facing features in software, IP and design methodology.

Triaged change requests against features. Tested usage scenarios, root caused the issue at hand and assigned it to the right developer for a proper fix in an appropriate release.

Wrote and maintained user-guides and reference documents for customer-facing documentation.

Created outbound marketing content in the form of videos, application notes and reference guides to help demonstrate features, ease-of-use and capabilities of software and tool flow.

Demonstrated new product features to cross functional teams and external customers.

Worked with new / existing customers to enable them jump start projects on Vivado / SDx / SDK /Vitis Tool Suites.

Recommended design methodology for packaging of IP, embedded designs including Zynq, MPSoC and MicroBlaze processors, PCIe, HDMI, and Ethernet, from design entry through software development.

Recommended design methodology for creating platforms that use C / C++ Kernels developed in Vitis tool suite for integration in Vivado IDE.

Provided use case scenarios for various features to help develop test plans for design verification team.

Avaya, Lucent Technologies and AT&T Denver, CO 06/1995 – 06/2012

Member of Technical Staff

Lead Designer for several multi-million gate FPGA designs incorporating several Intellectual Property (IP) Cores developed at Avaya including Embedded Processors.

Researched different device architectures for various ASICs / FPGA designs.

Planned and partitioned entire design at the RTL level, provided pin-out to PCB design teams, conducted functional simulation, synthesis, RTL gate level simulations and static timing analysis to ensure design correctness.

Naveen Dutta Page 2

Developed multiple IP Cores in VHDL providing GPIO, SPI, TSI and digital synthesizer functions and supporting telecommunication protocols (G.711, G.722 and propriety protocols). IP Cores were implemented in Altera Cyclone (I, II, III), Stratix, Xilinx Spartan III and Virtex devices.

Developed self-checking test benches incorporating file I/O and result comparison using QuestaSim for functional and timing verification.

Designed ASICs, including TSI function, gain adjusted conferencing and mu/A law conversion.

Designed several Altera and Xilinx CPLDs for high density circuit packs.

Reverse engineered several legacy ASIC designs into FPGAs.

Provided consolidation of several on-board components on legacy circuit packs into FPGAs, resulting in huge cost reductions.

Designed and developed several multi-layer circuit packs utilizing Motorola processors such as MPC860T, MPC68360, 68302 and Intel 8032. Developed board architecture, wrote technical documentation, and performed design entry, simulation, cross-talk analysis, thermal analysis and signal integrity.

Developed an end-to-end programmable logic design process for the AVAYA hardware development community. The process included creating protocols from conception of design to archiving completed designs. The entire programmable logic / ASIC design community throughout Avaya followed this process.

Wrote power-up boot diagnostics in C for complex circuit packs, simulated and tested it.

Negotiated, planned and scheduled tracking for entire project technical and non-technical items.

Metropolitan State College of Denver 09/2009 – 06/2012

Adjunct Faculty

Taught several classes including Digital Control Systems, Digital Logic Circuits I and III. Classes included lectures as well as labs to educate students.

Instructed logic design at an introductory level as well as at a higher level of abstraction using Hardware Description Language (Verilog) on Altera’s DE2 development boards.

Southern Illinois University at Carbondale, Carbondale, IL 06/1994 – 05/1995

Teaching Assistant

Assisted professors in Electrical Engineering courses. Helped with lab assignments, graded tests and assignments. Supervised students in lab.

Provided instruction in use of software including Matlab, Simulink and OrCAD.

Education

Master of Science in Electrical Engineering, Southern Illinois University at Carbondale, Carbondale, IL

Bachelor of Engineering in Electronics and Electrical Communications, Punjab Engineering College, Chandigarh, India

Tools

Linux, Unix, Windows Operating Systems

Mentor Graphics suite of tools (HDL Designer, Leonardo Spectrum, Precision Synthesis, Modelsim, QuestaSim, and Design Architect), Altera MaxPlusII, Altera Quartus II, Altera QSys, Altera DSP Builder, Xilinx ISE, Planahead, Vivado, HLS, SDK, SDx / Vitis Tool Suite, System Generator, Synopsis Synplicity, Mathworks Matlab, and Simulink

Documentation tools including MS Word, FrameMaker, Content Management System (CMS), Confluence, SharePoint and Git

Product planning tools including Jama and Jira

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