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Physical Design Engineer

Location:
Singapore, Central Region, Singapore
Posted:
February 27, 2020

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Resume:

DOAN NHAT THIEN ADDRESS:

**-***, ***** ***, ****** street 12,

Singapore 570111

PHONE:

+65 81303609

EMAIL:

adb0xi@r.postjobfree.com

PROFESSIONAL SUMMARY

* ***** ** ********** ** Custom Layout and 5 years of experience in Physical Design. Taking care of System- on-Chip block-level floorplanning, power structure, place and route, clock tree structure, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna). WORK EXPERIENCE

03/2015 - Present

Physical Design Engineer

Mediatek Singapore

Working at block level from verilog netlist to GDS: Making die size, ports assignment, floor planning, SRAM placement, routing and congestion/density solving.

Implementation low power design with Multi-voltage and large instance number (1M – 3M).

CTS analyzing: optimise clock latency/clock level for skew quality.

Experience on high frequency (~1Ghz) and multi power domain design.

Check timing correlation by STA and do ECO by PrimeTime/Tweaker.

Expertise in physical verification with Calibre/ICV (DRC, LVS, LVL, ANT, ERC, …).

Fixes Static and Dynamic IR.

Doing LEC and CLP verification.

Good at scripting with experience in Tcl.

Proficient in using tools such as ICC/ICC2, Innovus, Primetime and Tweaker.

Working experience on 28nm, 20nm, 12nm, 10nm and 7nm. 02/2014 – 03/2015

Custom Layout Engineer

Mirochip Technology Vietnam

Making floor plan, power maps and routing for flash memory.

Coordinate with Circuit Design team to get high quality layout.

Doing layout verification with Calibre (DRC, LVS, LVL, ANT, ERC, …).

Analyzing and fixes EM/IR issue.

Making test chip and do verification for test chip.

Having deep knowledge about flash memory and analog layout.

Proficient in using Cadence tools (Virtuoso, Composer, Calibre).

Making schedule to complete tasks ahead the deadline.

Working experience on 130nm, 65nm and 55nm.

DOAN NHAT THIEN ADDRESS:

04-152, block 111, Bishan street 12,

Singapore 570111

PHONE:

+65 81303609

EMAIL:

adb0xi@r.postjobfree.com

WORK EXPERIENCE

03/2010 – 02/2014

Custom Layout Engineer

Renesas Design Vietnam

Tuning schematic and making layout for In/Out cells.

Having deep knowledge about characteristics of CMOS.

Making floor plan, power maps and routing for In/Out cells.

Doing layout verification with Calibre (DRC, LVS, LVL, ANT, ERC, …).

Doing StarRC extraction and pre/post-simulation (VIOHL, delay, HBM, power on, ...).

Verifying and fixes EM/ESD by TOTEM tool.

Making Truth table and LEF data for all library of In/Out cells.

Making test chip and doing verification, simulation for test chip.

Doing cross check and peer review with team.

Proficient in using Cadence tools (Virtuoso, Composer, Calibre).

Working experience on 45nm, 28nm, 20nm and 16nm. EDUCATION

2004 - 2009

Bachelor Degree of Engineering, HUTECH university, Vietnam LANGUAGES

English : Very good command

Vietnamese : Native speaker

INTERESTS

Football: making team relation and good at working together.

Running, swimming: enhancing my health and trying to achieve personal challenge.



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