Kanukarthula Street, Vizianagaram-5
A dedicated, resourceful and innovative professional, seeking a role to utilize career experience, skills and education to contribute to employer objectives, profitability and success with a company offering potential for challenge and growth in R & D spectrum. Profile Summary:
Knowledge of physical design concept ranging from RTL to Tapeout.
Comprehensive understanding of methodologies of floor planning, place &route.
Exposure to timing closure and physical verification.
Familiar with ASIC back-end design methodologies and verification flows.
Hands on experience with Altera, Xilinx Vivado and Modelsim.
Experience in RTL Design, FPGA Prototyping and Functional Simulation.
Hands on experience of Zed board, FPGA Cyclone -1V, Spartan-3E&6,Basys3 Artix-7 and Virtex-7 FPGA boards.
Experience in test bench development in both VHDL/Verilog and its interface with DUT
Self -starter, enthusiastic and leading a team.
A highly motivated and strategically focused performer
An effective, innovative professional with strong analytical and problem solving skill
An excellent multitasking ability with outstanding organizational skills
Comfortable and self-confident in a diverse population
A passion for professional ethics and adherence to organizations core values. WORK EXPERIENCE
I. Industrial Experience: 03+ years
Presently Working as Application Engineer for Part time in APPLY VOLT Pvt.Ltd, Vijiayawada
Worked as Project Officer at National Institute of Electronics and Information Technology
(MeitY,Govt.of India) Chennai from 18th Feb 2015 to 17th Feb 2018. II. Teaching / Academic Experiences: 4.4 years
Worked as Assistant Professor in Dept of ECE, Avanthi's Research and Technological Academy, Bhogapuram( ARTB), from 20/06/2013 to 7/12/2013.
Worked as Ad_Hoc Lecture in Dept of ECE,University College of Engineering
(Autonomous -JNTUK) from 8/07/2012 to 20/05/2013.
Served as Assistant Professor and HOD (One Year) in Dept of ECE, Gokul Institute of Technology & Sciences (GITAS), Piridi, from 01/6/2009 to 6/7/2012. CURRICULUM VITAE
Project Detail :
Project Title 1 Asynchronous FIFO design with clock domain crossing in Verilog HDL Tools used Xilinx Vivado 16.1, ModelSim
To FIFO design with different clocks for read and writes operation. Write clock is faster than Read clock. Full and Empty condition generation using pointers and counters for incrementing the pointers. FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques.
Roles&Responsibilities RTL Design of the module, Test bench development, Simulation, Synthesis of the design
Project Title 2 Design and Implementation of Smart Watering System Tools used: Xilinx VIVADO 16.1 and Arduino Software Hardware used: Basys3 Artix-7 FPGA and Arduino
Objective: In this project, Build a smart watering system that will tell you when you need to water a plant based on the soil moisture, air temperature and light levels.
Roles & Responsibilities: RTL Design, Synthesis, implementation and verifying bit file on FPGA Academic Projects:
Project Title 1 Design and Implementation of Rc4 Stream Cipher for Wi-Fi Security Tools used VHDL, Xilinx 9.2i,ModelSim6.0a
To RC4 is one of the most widely used ciphers in practical software applications.RC4 uses a variable length key from 1 to 256 bytes to initialize a 256 byte array .the array is used for subsequent generation of pseudo-random bytes and then generates a pseudorandom steam, which is XORed with the plaintext/cipher text to give the cipher text/plaintext. Roles&Responsibilities RTL Design of the module, Test bench development, Simulation, Synthesis of the design
Project Title 2 Implementation of a MAC Based on radix-2 modified booth encoding algorithm
Tools used VHDL, Xilinx 14.6,ModelSim10.0,Cadence
Spartan 6 FPGA
The objective of a good multiplier is to provide a physically compact, good speed low power consuming chip. By combining multiplication with accumulation (MAC) and devising a hybrid type of carry save adder (CSA), then the performance improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. Roles&Responsibilities
RTL Design of the module, Test bench development, Simulation, Synthesis of the design and implemented on Spartan-6 FPGA Board. Minor Project :
Designed a project on Speed Control of D.C. Motor using Pulse Width Modulation Research Publications : 03 (International Journals, Conferences)
Paper entitled “Implementation of Smart Sensor with Frequency to Digital Convertor for Flow Measurement Using FPGA”. published in International Journal of Advanced Research in Science and Technology, Volume 1, Issue2, Dec-2012, ISSN 2319–1783
Paper published in ICNEA-11 (Built-in Self-Test for Communication Application).
Paper published in ICACM-11 (Design and Implementation of VLSI Architecture Accumulator Based on Redix-2 Modified Booth’s Algorithm). International Conferences/Workshops attend :
A Two-Days Workshop on” System Design on Zynq using SDSoC” conducted by IIT Madras and Corel Technologies Pvt.Ltd.
A Two-Days National Level Workshop on”Advanced VLSI Technology”
A Two-Days of 25th International Conference on VLSI Design and 11th International Conference on Embedded Systems at Hyderabad.
A Two-Days Workshop on ” System design using XILINX FPGA” conducted by Corel Technologies Pvt.Ltd,at GVP College of Engineering,VSKP
A Two-Days Workshop on” Advanced Embedded system design” conducted by Embedded Wings at Andhra University.
A Three-Days National Level Workshop on “Low Power and Mixed Signal VLSI” at Aurora’s Engineering College, Hyd.
A Three-Days Workshop on” Analog and Mixed Signal Design” conducted by CADENCE at JNTUH
M.Tech in VLSI System Design, Aurora’s Engineering College.
B.Tech in Electronics and Communication Engineering, M.V.G.R College of Engineering. Certifications: PG Diploma in VLSI &Embedded Hardware Design, NIELIT Calicut. TOOLS AND LANGUAGES
Domain Expertise: FPGA Design, RTL Design, Timing Closure (Debugging, Functional Board Testing, Programming & Configuration of FPGA), Embedded System Design, IoT and Arduino
RTL Languages: VHDL, Verilog HDL
EDA Tools: Modelsim, ISim, Quartus 12
Synthesis tools: Xilinx ISE, Vivado 2015.1, Cadence
Design Tools: Microwind, FLOTHERM 10, FLOTHERM PCB, Diptrace, Arduino, CCS DECLARATION
I hereby declare that the information furnished above is true to the best of my knowledge and belief.
Place: Vizianagaram ( M.RAJINEE)