Anmol Singh Narwariya
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Ward No.-13 Main Road Gormi, Dist.- Bhind, 477660
Area of Interest
Field Programmable Gated Array, Hardware/Software Co-design, Hardware Interfacing, Real- Time Operating System & Machine Learning.
2019 -- Present Project Assistant at CSIR-Central Electronics Engineering Research Institute, Pilani.
2017 -- 2019 M.Tech. in Embedded Syestem: Malaviya National Institute of Techno- logy, Jaipur
Thesis title: Real-Time Operating System Mapping for Task Performance Evaluation. In this Project, conﬁgured the Zynq(ZC702) board for Processing System
- Programmable logic Part and schedule the task according to real-time application and compare the task performance.
Minor Project: Street View House Number Recognition Using CNN. In this project, our task was to recognize arbitrary multi-digit Numbers from street view image. To achieve this proposed target, we had used CNN with multi hidden layers that operated directly on image pixels . Supervisor: Dr. Vineet Sahula (Professor, ECE, MNIT, Jaipur) 2013 -- 2017 B.E. in Electronics & Telecommunication Engineering: Jabalpur Engin- eering College, Jabalpur.
Major Project: Personal Weather Station
In this project, our task was small place environmental quantity (like tem- perature, humidity, pressure etc.) show on online interface. Minor Project: Automatic Water Level Controller
Any given pump set motor will Control the Operation of the pump set depending upon the water level in the source and destination storage tanks. 2011 -- 2012 XII (Higher Secondary Examination): Rajendra Convent Higher Second- ary School, Bhind.
2009 -- 2010 X (Secondary Examination): Rajendra Convent Higher Secondary School, Bhind.
Coding C, Python.
Operating Systems Linux, Windows.
Embedded OS FreeRTOS.
Multimedia Framework GStreamer,FFmpeg.
EX, Microsoft Oﬃce
Hardware Design Tools Xilinx-(VIVADO, FPGA Editor, SDK), Questa-Sim and Qucs.
Hardware Xilinx Zynq(Zc702), Artix-7 (Nexys 4 DDR, Basys 3). Knowledge of PMOD, XADC, Sensor, GPIO, PS-PL interfacing in Xilinx FPGA
2017 I got Excellent Grade in “VLSI Design Veriﬁcation Workshop”. 2010 I scored full marks in Mathematics (100 out of 100) in 10th standard. Extra Curricular Activities
2016 Coordinator: Coordinate in "Aureole’16" annual Techno-Cultural Fest held at JEC, Jabalpur.
2014 Coordinator: Coordinate in "Blood Donation Camp" held at JEC, Jabalpur. Workshops & Short-term Courses
Workshops & Short-term Courses
2018 EICT-Workshop: Academic Training Programme on "ANN & Deep Learning" held at MNIT, Jaipur.
2017 EICT-Workshop: Academic Training Programme on "VLSI Design Veriﬁcation" held at MNIT, Jaipur.
EICT-Workshop: Academic Training Programme on "CAD Tools For Advanced Digital Design Using FPGA’s" held at MNIT, Jaipur.
Dr. Vineet Sahula Dr. D. Boolchandani
Professor, ECE Professor, ECE
MNIT, JLN Marg MNIT, JLN Marg
Jaipur, 302017 Jaipur, 302017
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