Nirmal Sharma, PhD
Microelectronics Packaging Consultant
20+ years’ success leading microelectronics engineering innovation for high-growth organizations
Extensive experience with materials and processes in manufacturing of microelectronics packaging to maximize reliability and reduce costs in deadline-driven timelines. Expertise in microelectronics device fabrication, assembly process innovation, and problem-solving in high-volume manufacturing environments. Proven track record of technical leadership in continuous improvement of discrete transistor packaging in TO 220, SOT 23, and other power packages having multiple international manufacturing centers. In depth knowledge and understanding of potential failure mechanisms affecting packaging reliability. Hold 11 U.S. patents for technological innovations in microelectronics.
Highlights of Expertise
Six Sigma / Lean Manufacturing
High Volume Production
QC and QA
Cost Reduction and Revenue Increase
Packaging IP Generation
Risk Assessment and Management
Backend / Assembly
Astropack Technology, Fremont, California
A new innovative assembly and packaging consulting service providing Semiconductor and Microelectronics Packaging consulting services on new complex ICs, LEDS and MEMS devices simulation/prototyping/process development.
Managing Principal Packaging Consultant (2012 to Present)
Collaborate with clients, company CM, and material suppliers to develop and drive costs down through product simulations while maintaining performance and reliability. Clients include GE Sensing, Centallax, AOI, Tigo energy, and Across Silicon. Through intense design and testing procedures the team delivers products that achieve a first pass success.
Provide leadership to MEMS engineering team in areas of packaging design, materials selection, and structural analysis with the primary focus on sensors for automotive applications with emphasis on new materials and assembly methods.
Design package architectures for MEMS sensors, evaluate design robustness, draw technical conclusions, and make appropriate recommendations to ensure conformity with design intent.
Assemble prototypes, perform testing, analyze results with statistics, and perform tolerance analysis and FMEA through collaboration with global assembly manufacturers.
Improve assembly process flow and BOM through rigorous testing and correcting through DOE’s for resolution of qualification failures.
Increased yields at Centellax to 99% from a low of 10% within a week through on-site consultation and experiments to find root cause of the issue and provided corrective action.
Recovered several million dollars in lost revenues for Tigo Energy from component supplier by discovering cause and providing correction of a broken wedge bond that lacked a security bond.
Secured new business contract for GE Sensing by demonstrating zero leak failure through thorough testing and replacement of ceramic cap to LCP and using an epoxy that could sustain high temperatures, solving an issue competitor was having.
INPHI Corporation, Westlake Village, California
INPHI Corporation (NYSE: IPHI) is a leading provider of high-speed analog semiconductor solutions for the communications and computing markets, providing high signal integrity at leading-edge data speeds that are designed to address bandwidth bottlenecks in networks, minimize latency in computing environments and enable the rollout of next generation communications infrastructure.
Packaging Consultant (40G/100G MCM Hybrid Packaging/Assembly Processes), (2011 - 2012)
Developed business development strategies of Broad Band Analog Hybrid/MCM package for 100G pet III-V high power amplifiers and pre-amplifiers.
Achieved first pass success on package design through cross-functional collaboration with design team, packaging assembly, and BOM suppliers.
Evaluated, designed, and developed high-K epoxy to replace Au/Si die attachment based on outgassing, ionic content, and stability of thermal and electrical conductivity at high operating temperatures.
Provided leadership in SMT process automation and design optimization for thermal management, environmental, and RGA manufacturability.
Improved die attach process significantly through elimination of resin bleed from die attach epoxy.
Allegro Microsystems Inc., Worcester, Massachusetts
A leading developer and supplier of advanced mixed-signal analog power IC semiconductors and current sensor ICs.
Director, Microelectronics Packaging (2004 to 2011)
Developed strategic power packaging roadmaps and manufacturing strategies for consumer industrial and automotive sensor products. Resolved critical reliability issues to maximize reliability in high volume digital microelectronics device manufacturing and assembly worldwide through root cause failure analysis, new designs and process adjustments.
Developed Sensor and Power Management packaging roadmaps to convert large footprint to smaller thermally efficient designs with low Rdson and without die design revision.
Obtained three product patents for array bumping for low Rdson, Copper pillar, and innovative Lead Frame designs using QFN flip chip current sensor packaging for high rel automotive distribution.
Decreased manufacturing costs by (insert %) transferring in-house packaging manufacturing to low cost suppliers in China and Malaysia.
Designed, evaluated, and produced plastic-molded Flip Chip Current Sensor package in only 18 months, adding $50M in revenue over five years.
Produced $15M in revenue within 18 months through participation in design, evaluation, and qualification of first 9-wafer level chip scale package WLCSP products with smaller footprint for Hall cell-based switch sensor used in cell phone application for Motorola and Samsung utilizing lead-free solder bump.
Led a team in planning, designing, evaluating, and qualifying industry’s first automotive crank sensor packages with integrated capacitors for EMC protection, resulting in projected revenues of $50M within four years for companies EFI and Bosch.
Senior Manager Packaging and Assembly Engineering Peregrine Semiconductor, San Diego, California
Director of Process Development Bit Blitz Communications Inc., Milpitas, California
Process Engineering Manager ST Assembly Test Services Inc., Milpitas, California
Senior Manager, Packaging and Assembly Operations Cypress Semiconductor, San Jose, California
Education & Credentials
PhD in Ceramic Engineering
University of Illinois at Urbana, Champaign, Illinois
Master’s in Ceramic Engineering
University of Illinois at Urbana, Champaign, Illinois
Bachelor’s in Ceramic Engineering
Institute of Technology, India
Certificate in the Management of High-Tech Companies – AEA Stanford University
US Patent 9228860 B2: Sensor and method of providing a sensor
US Patent 8461677: Magnetic Field sensors and methods for fabricating the same
US Patent 8486755: Magnetic Field sensors and methods of fabricating magnetic field sensors
US Patent 8143169: Methods for multi-stage molding of integrated circuit package
US Patent 7816772: Methods and apparatus for multi-stage molding of integrated circuit package
US Patent 7361531: Method and apparatus for flip chip on lead semiconductor package
US Patent 6995315: Current sensor
US Patent 6861283: Package and method for integrated circuit with thermal vias
US Patent 6809416: Package and method for integrated circuit with thermal vias
US Patent 6420779: Lead frame-based chip scale package and method of producing
US Patent 4731701: Integrated circuit package with thermal path layers incorporating staggered thermal vias