Self-motivated, reliable and adaptable MSEE with one-year work experience working for a major defense contractor. Excellent interpersonal and communication abilities. Strong multi-tasker able to handle simultaneous design and support tasks with full accuracy and efficiency. Possesses the analytical abilities and technical skills necessary for engineering innovative designs and applications. Enjoys interfacing with other engineering disciplines and expanding knowledge base. Has solid understanding of electrical engineering theory, industry-standard circuit design and testing tools.
EDUCATION: California State University, Sacramento • 6000 J Str. Sacramento, CA 95819
Master of Science, Electrical and Electronic Engineering, May, 2010
GPA: 3.16 • GPA (Last 2 Years): 3.32 • GPA (in Major): 3.54
Bachelor of Science, Electrical and Electronic Engineering
RELATED COURSE WORK:
Passive/Active Microwave Circuits
Analog & Mixed Signal IC Design
CMOS & VLSI Design
Semiconductor Device Physics
High Speed RF Electronic Systems
High Speed Digital Design
Digital Signal Processing
Fiber Optic Communications
RF Circuit Design
Signal Integrity Engineering
Digital Logic Design
Office Applications: Microsoft Office (98, XP, 2000 and 2003) and Open Office
Programming Languages: C, C++, Perl, Python, Tcl, MatLab, RTL verilog, VHDL and 80X86 Assembly Language
Operating Systems: Windows (2k Pro, XP, XP Pro, and 7), Mac OS X, Linux and UNIX
Circuit Design Software: SPICE, PSPICE, Cadence OrCAD, Ansoft Designer, HFSS, Advanced Design System: ADS, Synopsys VCS, Synopsys Design Compiler, Simulink, Mentor Graphics Design Architect, Mentor Graphics IC Station, Mentor Graphics ModelSim SV, Xilinx ISE, Altium, AutoCAD Electrical, Zuken and Altera Quartus II.
Electronic Laboratory Equipment: Oscilloscope, DC Power Supply, Function Generator, Digital Mulitmeter, LCR meter, Logic Analyzer, Network Analyzer, Curve Tracer, Spectrum Analyzer, microcontroller or FPGA development boards.
MASTER’S PROJECT: A TAPERED CML BUFFER CHAIN DESIGN FOR A 1 GHz ADC
Was part of a team of five engineers designing a 6-bit interpolating flash ADC operating at 1 GHz. Responsible for the design and layout of the output driver for the ADC. The design process included weekly status reports to the team lead, an architectural design review (ADR), a preliminary design review (PDR) and a layout review.
Designed and simulated a Tapered CML Buffer Chain for the ADC.
Used Mentor Graphics Tool Design Architect for schematic capture and simulation.
Used the Mentor Graphics Tool IC Station for the circuit layout, DRC and LVS of the Tapered CML Buffer Chain.
Both a design review and a layout review were conducted by the instructor and team lead during the design process.
At the conclusion of the project a report discussing the design procedure, simulation results and layout of the tapered CML Buffer was submitted.
Published Project Report in Scholar Works technical database.
Electronics Engineer 06/15/2016 to 04/30/2018
Lockheed Martin Space Systems • Sunnyvale, CA 94088
Responsible for: engineering production, re-qualification activities, hardware tests, deployed system support, failure analysis and maintenance of component/system specifications.
Takes ownership of design, analysis, and interface documentation for the Fleet Ballistic Missile (FBM) Space System Company Program Avionics Test Missile Kit (TMK).
Engineering Delegate that provides technical oversight and/or direction to the subcontractor and works with other FBM teams like Quality Assurance and Systems Engineering.
Independent contributor and member of multidisciplinary team that ensures successful integration of the packages and compliance of the product with all program requirements.
Maintains Weapon Specification and other Technical Documentation including mechanical and electrical drawings.
Performs technical evaluation of design and requirements.
Interfaces with Quality Assurance to make sure that all failure analysis procedures and tests are compliant with relevant technical documents.
Aides Program Management in technical evaluations for fiscal year proposals.
Leads Failure Analysis teams to closure of investigation. Completes critical electrical tests utilizing electronic laboratory equipment, timing and/or data acquisition systems, performs data analysis on test results and supports other failure analysis efforts performed by external agencies.
Conducts: Status Reviews, Technical Interchange Meetings (TIMs), delivers technical and/or scientific presentations to management, authors technical and/or scientific reports/papers and participates in Flight Readiness Reviews (FRRs).
Reference Librarian Assistant, March 2007 to June of 2009
San Joaquin County Public Library • Stockton, CA 95210
Managed library reference resources.
Helped patrons with the use of library computer resources.
Aided library patrons in locating reference books.
Aided library patrons using other library system resources.
Shelved returned reference books.
Sales Associate, February 1995 to August 2003
Sears • Stockton, CA 95207
Counseled customers on computer purchases.
Provided training for new and existing employees.
Monitored and maintain display computers.
Worked with Sales Managers to establish department goals.
RELATED INDIVIDUAL PROJECTS AND EXPERIENCE:
Microwave Devices and Circuits: Circuits designed using ADS and Ansoft Designer SV
Active Microwave Circuits: Designed low noise amplifiers, power amplifiers and oscillators.
Passive Microwave Circuits: Designed impedance matching networks, filters and LC resonant circuits.
Signal Integrity Engineering:
FDTD Simulation of Microstrips: Used Maxwell 2-D to calculate the self-capacitance, mutual capacitance, self-inductance and mutual inductance of two microstrips using finite element analysis. The Electric Field plot was generated based on the Maxwell 2-D simulation results.
CMOS and VLSI Physical Design:
Physical Design: Designed standard cell circuits like: static logic gates, dynamic logic gates, complex logic gates, latches, flip-flops, adders and multiplexers. Also designed custom cells.
Designs were required to be DRC/LVS clean and meet timing/area specifications.
Analog and Mixed Signal IC Design: Circuits simulated in Cadence OrCAD
Analog Circuits: Designed transistor level circuits for current mirrors, bandgap references, CMOS amplifiers, CMOS op-amps and comparators. Also simulated DAC and ADC circuits.
Miller Op-Amp: Designed and simulated a two stage Miller Op-Amp. Computed compensation capacitor value, dc bias currents of MOS devices, W/L of MOS devices, voltage gain and power dissipated. Plotted frequency and transient responses of Miller Op-Amp.
Designed 4-bit Interpolating Flash Analog to Digital Converter.
Digital Logic Design:
Built FPGA development board to complete course projects.
Arithmetic Logic Unit: Designed, simulated, and synthesized an 8 bit ALU in RTL verilog that implemented four functions: AND, OR, add and subtract using Synopsys VCS.
Digital Logic Circuits: Designed and simulated finite state machines, comparators, decoders, counters, shift registers, clock dividers, adders, subtractors, multipliers and dividers in RTL verilog and VHDL using Synopsys VCS. Also implemented logic circuits in ModelSim SV.
Digital Signal Processing: Filters designed using MatLab and Agilent ADS
Short Time Fourier Transform: Gave a technical presentation of the Short Time Fourier Transform using MatLab and MS Office. Also designed Kalman filter.
Filter Design: Deigned low-pass filters, high-pass filters, band-pass filters, band-stop filters, Butterworth filters, Chebyshev filters, adaptive filters, FIR filters and IIR filters.
CMOS Fabrication Process Simulation: Modeled Ion Implantation, Diffusion, Oxidation Thickness and Oxidation Rate Constant using MatLab.