Engineer Design

RAUSHAN KUMAR Ph: - 916-***-****

https://www.linkedin.com/in/raushan-kumar-3132a6133/

*************@*****.***

OBJECTIVE: Seeking Full-Time/Contract position in ASIC/SoC Design Verification/Validation/FPGA. Two years hands on Experience in ASIC/FPGA design and Verification Domain, hands on experience including RTL Design, Verilog HDL/ System Verilog, UVM, Code Coverage, Static Timing Analysis (STA), Functional Coverage, Assertions (SVA).

EDUCATION:

MS in Electrical and Electronics Engineering, CSU Sacramento, CA (Aug/2016 – Dec/2018) B.Tech in Electronics and Communication Engineering, SHUATS, India (Jul/2010 – May/2014) TECHNICAL SKILLS:

Language: Verilog HDL, System Verilog, C++,

Object Oriented Programming

Verification Methodologies: UVM

Hardware: Xilinx Spartan 3E FPGA, Arduino

Development Board

Tools: Synopsys VCS, QuestaSim, ModelSim

Simulator Mentor Graphics, Cadence Virtuoso,

Design Compiler, Cadence Pspice, Xilinx ISE,

MATLAB, Simulink, EDA Playground

Scripting Language: PERL/ tcl

Operating System: Linux, Unix, Windows,

Mac

Protocols: DVS, MESI, UART, SPI, DDR

Architecture: Concept of Pipeline and Hazards,

Addressing Mode, Cache, Cache Mapping,

Virtual Memory, Paging,

Work Experience:

ASIC Verification Engineer – Synapse Business System (Jun/2014 – Jun/2016)

Created UVM environment, registering all the UVM component items UVM Object items to factory, creating master agent, slave agent, Driver, Monitors, scoreboard. Passing transaction items through TLM port from Sequencer to Driver and passing Transaction to DUT via Virtual Interface and checking/comparing output result from input/output monitor to scoreboard via analysis port.

Created UVM test benches and environment. Direct Test were used to check the hard corner cases and Constrained random variables were used to cover most verification Space. Score boards were used to compare in and out of order transactions. Functional coverage was used to verify the functionality of Design under Test.

Writing direct testbench, self-checking testbench, constrained random testbench in Verilog/ System Verilog

UVM test cases with sequences and Factory methods to create modular and reusable test bench components

Created UVM components and test cases to separate structural from behavioral for reuse. Constrained random stimulus were created, sequences to stimulate the DUT. Driver and Sequencer were synced with the TLM

Scoreboard was used for self-checking along with assertions to check corner cases. ASIC Design Verification Engineer - Verifast (Aug/2018 – Aug/2019)

My work was related in designing the DUT and develop the hardware and writing the test fixture, writing multiple test cases to check and verify the functionality of the design and debugging the scripts.

Experience in Implementing test bench, self-checking, direct testbench in Verilog and system Verilog also worked independently to debug the RTL and find the bugs by creating multiple test cases.

Creating System Verilog Environment with Generator, Driver, Input/output Monitor, creating scoreboard, Transacting packets from Generator to Driver via Mailbox and checking the results in Scoreboard

Cross check the behavior of the DUT by looking at waveform and rerun the test cases to check and verify the behavior of the design.

Introducing bugs in the design and checking the functionality and behavior of our DUT ACADEMIC PROJECT:

[UVM] [System Verilog] Design Verification of Memory Controller • Tool: QuestaSim & EDA Playground

Designed a register having 8 bit wide 32 bit deep memory.

Designed the testbench in System Verilog and verified using UVM based environment

[UVM] [System Verilog] Design Verification of 4x4 Router • Tool: QuestaSim & EDA Playground

Designed a 4x4 Router and designed the test bench in System Verilog and verified it using UVM verification environment which consists of environment, scoreboard, sequencer, driver, input monitor, output monitor that can sample accordingly.

[System Verilog] Design of UART protocol • Tool: QuestaSim

Designed Implementation of a UART protocol, developed a verification plan and wrote multiple test case to check the functionality of the UART protocol.

Generated and analyzed the waveform in QuestaSim Simulator

[System Verilog] Design Verification of a fsm Calculator by DVS Protocol •Tool: QuestaSim

Designed Verification of a two state fsm sequential calculator which uses a Data-Valid-Stall (DVS) Protocol,

Based on Constrained Random Self-Checking Architecture, I modelled the calculator in using RTL design and built a testbench to simulate and verify my DUT

[Verilog HDL] Project on Memory Controller • Tools: VCS & ModelSim

Designed of memory model and wrote test bench using self-checking mechanism in Verilog HDL

Wrote multiple test cases and check the functionality and behavior of our Design cross verified by checking the waveforms.

[Verilog HDL] Design, Verification and Synthesis of Floating Point ALU • Tool: VCS Synopsys

Designed a data path of Floating-point Addition, handling single precision floating point numbers expressed in IEEE 754 format.

Modelled a FPALU and in Verilog using RTL. Designed and developed an automated testbench for validating it analyzed the synthesized circuit using tools and generated code coverage report.

[Verilog HDL] Design and Implementation of Digital Watch •Tool: ModelSim

Designed, Modelled and simulated a Digital watch. This project involves in developing the Digital watch using multiple counters.

Draw hardware and modelled a digital watch in Verilog using RTL design and simulated multiple test cases to check all the corner cases and verified all the outputs in waveform. Project on PERL Automation, TCL • Tool: Synopsys VCS and DC Compiler

Designed various Verilog, RTL design and Perl programming such as Ripple Carry Adder, Up- Down Counter, Memory unit and ALU understanding the concept of automation by creating testing input and output data using Verilog programming.

Generated various Timing reports using Tcl and Synopsys tool scripting language. Also analyzed the generated netlist for optimization of area, timing and power report. Design and Layout of Synchronous 4-bit FIFO with Empty/Full Indicator •Tool: Cadence Virtuoso

Designed control logic and memory circuits for a 4-bit 6-Entry FIFO buffer. Simulated the logic design in Cadence Virtuoso tool as per specifications.

Developed a schematic design and layout with specific design rule.

Performed DRC and LVS over the design.

FPGA based Design, Synthesis and Simulation • Tools: Xilinx Spartan 3E board

Designed, synthesize and simulate of a mod4 modN counter, Elevator, Vending Machine using Verilog RTL. Passed multiple input vector in our testbench to check DUT and verify design by looking at waveform on Xilinx Spartan 3E board.

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