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Design Project

Noida, Uttar Pradesh, 201304, India
September 13, 2019

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Phone no: +918*********, 846-***-****.

Email id:

Career Objective

To work in a friendly environment where I can apply and enhance my skill, my energy, my time to serve the firm to the best of my effort and also enhance my skills along with the growth of organization.

Experience Summary

I am working as an Executive Engineer in FIBCOM INDIA LTD NOIDA from March 2017. Work Experience Detail

Job profile: Design, Validation & ATE developer

Department: Research and Development (R&D-Hardware) Key Responsibilities Handled:

Schematic Design in ORCAD(capture).

Analog design/ Embedded Hardware design and simulation.

Hardware design planning (selection of devices, Interfaces & Peripherals).

Prototype PCB board bring up.

Test plan and perform testing & validation of design .

Generating the component requirements and specifications.

Generating BOM and analysis obsolescence risk for design.

Automatic test planning and development using NI TestStand,NI LabVIEW.

System level Boundary scan test(Infra, Inter, Cluster, RAM, Manual test) planning and Development using Gopel Cascon 4.2.

Debug activities including board level using Oscilloscope, Multimeter etc.

Timing analysis and analysis of system level functionality.

Providing the layout guideline to the PCB designer .

QM333 /EMI EMC Testing planning and support for product.

Techinical review and technical documentation.


Project 1: SIMX16M-7 module Design

Description SIMX16M-7 is PCB module developed for Cross-Connect in 6335 SC3 sub rack .Six channel cross connect module with one SAP6,5G higher order capacity and 10G lower order capacity. The top level design of simx16M-7 contains FPGA, ASIC, CPLD,PHY and EEPROM.

My Task- Design schematic(ORCAD Capture), create net list file,Generate BOM.

Boundary scan chain from schematic /Automatic test development & debugging (inter,infra,cluster,manual and ram test,CPLD/FPGA programming) using Gopel Cascon 4.2 .

The whole proto board bring-up process.

Test planning and perform all module test.

ATE job prepare using NI TestStand, LabVIEW.

Project 2: EMAP8S/EMAP8SF-W/EMAP8S-2 module Design Description EMAP8S,EMAP8S-W&EMAP8S-2 are PCB module, which are able to mapped and switch the Ethernet data with capacity of 2.5G. Used to map Ethernet data over SDH data. The top level design contains DC-DC Converter,FPGA, ASIC, CPLD, DDR3,DDR2,QDR2,TPW48,Vitesse,PHY,EEPROM,flash(Nor&Nand),winpath3,LDO.Se rdes,XAUI,SPI3 interface.

My Task- Design Document(Block Diagram) create .

Selection of components (DC-DC converter/LDO,vcxo,tcxo,and other discrete components and IC).

Design schematic(ORCAD Capture), create net list file,Generate BOM.

Hardware simulation.

Boundary scan chain from schematic /Automatic test development & debugging (inter,infra,cluster,manual and ram test,CPLD/FPGA programming) using Gopel Cascon 4.2.

The whole proto board bring-up process.

Test planning and perform all module test.

ATE job prepare using NI TestStand, LabVIEW.

Project 3: DC-DC converter testing/Validation of TCXO,VCXO. Description 1-As per ITU-T Standard we are using power supply modules which used to convert 48V to 12V. So, we are using DC-DC convertor with load sharing and redundant feature.

2-For the designing process I had to validate the major devices, which are to be mounted on the PCB.

My Task- To test the critical specifications such as Input voltage and output voltage level.

Power consumption, ripples observed on the output, load sharing, inrush current, Thermal parameters and redundant feature.

Validate the functional and behavioral characteristics as per our design requirements.

Project 4: LINE EDFA_BA Module Design.

Description EDFA is PCB module, developed for optical amplification. The top level design of EDFA_BA contains FPGA, OFA, EEPROM,FLASH,MAX232 and other discrete components.

My Task- Design schematic in ORCAD(capture)., Bom, netlist from schematic.

FPGA Loading, UART Interfacing,I2C interfacing.

The whole proto board bring -up process.

All basic module testing including thermal test.

Ate development for all basic and functional test . Project 5: Thermo Amplifier PCB review & Testing . Description Thermo Amplifier is a module which provides output voltage according to the temperature. This module has simple circuitry consists of Temperature Sensor, Comparator, Transistors, Zener and DC-DC converter. My Task- Design schematic in ORCAD(capture)

Generate BOM,gerber file,netlist file.

Review Pcb using allegro pcb editor.

Board bring up and all basic hardware test.

Automating Fluke Cold Bath for Real time testing of UUT. Project 6: RD BOARD for thermoamp design & testing . Description RD BOARD is PCB module for testing, which is able to test 8 thermo amp at a time.The top level design of RD BOARD contains FPGA, CPLD,Atmega32,ADC,Digital potentiometer,flash and EEPROM.

My Task- Selection of components for the design and making BOM.

Design schematic in ORCAD(capture).

Generate BOM,gerber file,netlist file.

ATMEGA 32 interfacing(SPI,I2C,UART) .

ATMEGA 32 Programming and debugging using avrstudio5 and Protius7.

Board bring up and all basic hardware test.

Boundary scan chain from schematic /Automatic test development & debugging (inter,infra,cluster and manual test.

Skill Summary



WINDOW- 07 08,10 and LINUX

FPGA & CPLD: ALTERA-Stratix, Cyclone V and lattice-Mach.XO,XILINX-Spartan6 Processors





Basics of C,Embedded C,Assembly Language, Linux, Shell,TTL scripting,Python,Bash.





Interfaces :


Other devices: PHY, VCXO,TCXO,ADC,DAC,LDO,DC-DC converter. EDA tools: ORCAD, Allegro PCB Editor, Allegro PCB Viewer, Web-bench(Texas Instrument), EDAbase, Valor (PCB Viewer), Proteus,,AVRStudio5,Hyper Lynx . Test Automation


NI TestStand, NI LabView, Gopel Cascon4.2

Other tool: SAP,Microsoft VISIO, AG2, Extended Craft Terminal,GIT. Hardware tools: SDH & Ethernet Analyser, Linux Ethernet tester, CRO, OPTICAL Power Meter, Optical Attenuator, Digital Counter, Digital Generator, Analog & Digital Multimeter, SFX-PCI TAP2, PIckit2, ISP programmer. Other skills: SDH, PDH, Ethernet, Boundary scan (JTAG). Educational Background

Year Qualifications Board/University College %

2016 PG-Embedded System Design C-DAC Noida CDAC 66% 2015 B.TECH


Uttrakhand Technical


UIT 68.7%

2010 10+2 Board of school

Education Uttrakhand

G.I.C Garur 57.8%

2008 10th Uttrakhand Board V.V Mandir 70.8%

Academic Project:

TITLE: -Vehicle security system : Using 8051 Microcontroller (B. TECH 4TH YR)

Abstraction: - This project is for security purpose.In this project loud alarm and sms generated by GSM Modem . Use of Embedded C-programming in binary with help of EDA tools Proteus

(use for embedded design) and Avrstudio5 (use for c-programming). Training & Technical skills

Summer Training in B. Tech 4nd Yr: - Undergone 1 month summer training on Satellite Communication from ONGC Deharadun.

Undergone 3 month training as a NTTF student in Engine Head Department from Ashok Leyland pantnagar.

Attend 1 week training on Embedded system Design by Multisoft Dehradun. Extra Curricular Activities/Other experience

Participate in various Skill Development Programs(PMKVY) Run by Government of India and Skilled 130 students with my Team from July 2015 to June 2106.

Yoga and Fitness Club Member.


Playing Cricket & TT

Gyming & cycling.

Personal Profile:

Date of birth : 21 March 1993

Father name :B.P Goswami

Address :Village/Post-Garur,district Bageshwar,Uttarakhand Declaration:

I hereby declare that all the above information is true to the best of my knowledge and belief. Place:

Date: (Manish Goswami)

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