Engineer Design

Saurav kumar

Bengaluru,karnataka,India -******

Email:- ******.****@*****.***

Contact No:- 833-***-****

Professional summary:

● 1year (AMTS) experienced layout engineer

● Proficient in Custom Analog and Digital layout design

● Experience in using industry standard EDA tools for the ASIC layout Design & verification.

● Posses good communication & presentation skills. Education:

2018:- Bachelor of Technology (electronics & communication) with DGPA 8.87 from Institute of Engineering and Management,kolkata (affiliated to West Bengal University of Technology)

2013: Higher Secondary from O.P Jindal School,patratu (84%) 2011: secondary from O.P Jindal School,patratu (CGPA-10) Technical Skills:

● Layout Design

● Memory architecture

● Memory layout

● Floor planning,routing & area estimation

● Spice simulation

● Standard cell Characterisation

● Verilog fundamentals

● Shell scripting

● Linux

Experience:

Dxcorr Design Inc.,Bangalore - Layout Engineer (Sept 2018 – Present)

● Good Knowledge of cmos fundamentals.

● Fundamental Understanding of finfets.

● Good understanding of SRAM Bitcell.

● Experience in optimized layout design for leaf cells & complex block in samsung 28nm fdsoi,GF7nm,Intel 22nm,samsung 7nm.

● Physical Verification checks like DRC,LVS,DFM,EM,IR.

● Matching techniques(Common Centroid and Interdigitation), Anteena effect, ESD techniques

● EDA tools: Cadence Virtuoso,Mentor Graphics Calibre Projects:

Sram:

Technology - Intel 22nm

Role: leaf cell layout designer

Responsibilities : layout design for decoder slice block, Array, leaf cells. Physical verifications checks like DRC, LVS

Mram:

Technology- Samsung 28nm fdsoi

Role: Analog layout Designer(Mixed signal)

Responsibilities: floor planning and layout design for Oscillator,Bias Generator block(BGR), Clock Monitor and Bias monitor block. I was responsible for layouts of Current mirror,Differential pair, level shifter, Opamp(two stage). Digital leaf cells:- Inverter, Nand, latch, Flop

Physical verification,EM,IR.

SERDES(R &D):

Technology- Samsung 7nm

Role: Leaf cell layout designer

Responsibilities: layout design for leaf cells like Inverter,nand,latch,Mux in 7nm node.

Analog layout for Current mirror,Differential Amplifier,Opamp (two stage). Physical verifications checks like DRC, LVS.

Personal details:

Date of Birth : 15th september 1995

Gender : Male

Languages Known: English,Hindi

Nationality : Indian

Declaration:

I hereby declare that the information furnished above is true to the best of my Knowledge. Place:Bengaluru Saurav Kumar

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