Komal Mankar
Master of Technology
(VLSI and Embedded System Design)
Email ID: ada39x@r.postjobfree.com ada39x@r.postjobfree.com LinkedIn Profile : www.linkedin.com/in/komal-mankar-28443010b Mobile: +91-968*******,+91-976*******
Career Objective:
Wish to work in a challenging and creative environment where I can apply and enhance my knowledge and skill which would enable me to grow while fulfilling organizational goals. Educational Qualification:
Pursued M. Tech (VLSI and ES Design) in SGGS Institute of Engineering and Technology, Nanded, Maharashtra
Exam College/ Board Percentage/
SGPA/GPA
Year of passing
M. Tech SGGS Institute of Engineering and Technology, Nanded (M.S.) 8.26 2019
BE(E&TC) Govt. College Of Engineering Karad (M.S.) 68.00 2015 HSC Maharashtra State Board Of Secondary and
Higher Secondary Education Pune
74.00 2011
SSC 91.38 2009
Projects Undertaken:
M. Tech (Sem III & IV) :
Title: Fast, Energy Efficient Approximate Multiplier Using Carry Maskable Adder and its FPGA Implementation
Duration: 12 months
Tool used: Xilinx ISE 14.7 Design Suite, FPGA (Spartan 3E) kit Description: Approximate multiplication is considered to be an efficient technique for trading off energy against performance and accuracy. This project proposes an accuracy- controllable multiplier whose final product is generated by a carry-maskable adder. The proposed scheme can dynamically select the length of the carry propagation to satisfy the accuracy requirements flexibly.
M. Tech (Sem II) :
Title: FPGA implementation Of Radix 8 Booth Multiplication Algorithm for high speed arithmetics
Duration: 4 months
Tool used: Xilinx ISE 14.7 Design Suite, FPGA (Virtex 7) kit Description: The modified algorithm reduces the number of partial products by the factor of 2, thereby improving the performance of the system. Page 2 of 3
M. Tech (Sem I) :
Title: Layout design, DRC, LVS, Parameter Extraction and post layout simulation for CMOS Inverter and basic logic gates
Duration: 4 months
Tool used: Cadence Virtuoso
Description: This project demonstrates the physical design, design rule check (DRC), parameter extraction, and layout vs. schematic (LVS) using the Cadence tools. And after parameter extraction, based on extracted parameters post layout simulation is done. B.E.(Electronics and Telecommunication)
Title: Intelligent, driverless metro rail prototype using ARM controller. Duration: 10 months
Team Size: 4
Tool used: 89C51 microcontroller, RFID module, GSM modem, GPS tracking unit Description: The project evinces an embedded system that controls the functionality of the metro train by means of various functions provided, without the need of manpower. Coursework :
1. Advance Verification Techniques
using System Verilog
2. Real-time OS
3. Analog Mix Signal VLSI
4. Low Power CMOS IC Design
5. Modern Digital Design Using
Verilog
6. Digital Integrated Circuit Design
7. Embedded System Design
8. Microelectronics
9. Reconfigurable computing and
System on Chip
10. Mixed Signal Hardware Design
11. Cyber Security
Conferences and Workshops:
1. Attended 31st
International conference on VLSI Design & 17th
International conference on
Embedded Systems held in Pune, January 2018.
2. Attended 1-week workshop on “ANALOG IC DESIGN” using Cadence Virtuoso conducted by ENTUPLE Technologies in December 2017.
3. Attended 1-week workshop on “VLSI DESIGN – BASICS TO ADVANCED” in March 2018. 4. Participated in Hackathon organized by Cadence Design Systems at VLSID International conference.
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Technical Skills & Proficiencies:
Hardware Description Language Verilog, System Verilog, Overview of UVM flow
Programing Languages C, Embedded C
Software Used Cadence Virtuoso, Questa-Sim, Xilinx ISE, Model-Sim, Keil Compiler, Proteus
OS Platform Windows, Linux
Personal Details:
Name Komal Chakrapani Mankar
Gender Female
Date of Birth 09/01/1993
Languages known English, Hindi, Marathi
Marital Status Unmarried
Nationality Indian
Permanent Address Vidya nagar ward, Panchashil chowk, Ballarpur- 442701,District: Chandrapur(M.S.)
Place: Pune
Date: 10/11/2019 (KOMAL MANKAR)