C++ Asic Design

Sunil Mahajan

Location: Cupertino, CA; Cell - 408-***-****

Professional Summary

• Accomplished ASIC Design/Verification Lead with in-depth expertise in RTL verification, emulation, design and lab bring up for multiple successful tapeouts and many more as an individual contributor. Known as detailed oriented and thorough, with good communication skills and able to work effectively both within and across teams.

Technical Skills

Languages

• Verilog, System Verilog, UVM, C, C++, Perl, Python, TCL, UPF, Shell scripting. Simulators/Emulators

• VCS, NcVerilog, MVSIM and native power. Emulators like Palladium, Zebu. Waveform viewers like Signal Scan, Debussy, Verdi, etc. Palladium Z1, XP series. Verification Skills

• Directed and constrained random methodologies, Functional and code coverage, Assertions, Formal verification using SVA, Gate-level simulation, GLS, SDF, Debug RTL and bringup chip in lab, develop and execute test plans, Timely execution.

Technology and Interfaces

• SOC, PCIE, ILA, Ethernet, NVMe, MPEG, Video, 3D Graphics, PC subsystem, DDR, AMBA, AXI, AHB, SPI Education

• Master of Science in Computer Engineering Villanova University 1990

• Bachelors in electrical engineering GIT India 1985 Professional Experience

Verification Consultant @ Groq June 24 - Now

• Verify Integrated System Testing controller for memories inside the chip. Verification Consultant @ Facebook Mar 24 - June 24

• Maintain the Palladium farm setup, installation, and upkeep for the Facebook Infrastructure group. Modify the palladium environment to include self-test for Lauterbach so the firmware group can be sure the setup is good for development.

Verification Consultant @ Tesla Jun 23 - Dec 23

• UVM environment, test plan and implementation for Voltage Droop Detector.

• Write testplan and create a module level uvm tb to verify Droop detector. Modify the UVM environment to add droop detector agent, to nearly 8 test benches(8 blocks spread out throughout the chip). These testbenches varied from module level, subsystem level to chip level testbenches. Verification Consultant @ Xconn Systems. Jan 23 - Jun 23

• Create module level UVM environment, test plan and implementation for Fabric Module Manager block for CXL 2.0

Verification Consultant @ Moneta Systems Feb 22 - Jan 23

• UVM environment, test plan and implementation for a Bitcoin chip.

• Bootstrap verification environment for Bitcoin chip in a startup that involved developing UVM environment from scratch, test plan, implementation, coverage for a Bitcoin chip. GLS with SDF. Verification Consultant @ Facebook AR/VR Apr 20 - Feb 22

• Chip and System level verification of chips that will go in the AR/VR platform. Verify both the graphics and the video pipeline at chip level and run the vectors on Zebu and bring them up in the lab.

• Chip and System level verification of chips that will go in the AR/VR platform. Create a system level environment that included two chips interacting with each other and working like it would in a real system. First bringup that combined environment, get a few tests working and handoff to the module level team that would run their vectors on this system. Do the same for emulation bringup on Zebu. Run both the graphics and the video pipeline vectors at this level on Zebu. Sr Principal Engineer @ Netlogic/Broadcom Inc Nov 2011 – Jan 2020

• Algorithmic Lookup/Search Engines. Combination of TCAM and algorithmic SRAM lookups. Cloud infrastructure chips.

• O3: A0-Block verification: RPT/PCT verification. Setup Power gating flow for design and verification. B0: Verification Lead. Module and chip level sims. Both module level and chip level Gate level sims (GLS).

• OP Verification Lead/Emulation

• Setup initial flows and manage different block level verification.

• Full chip verification application cases and performance tests including GLS and SDF.

• Emulation Lead. Setup. First time emulation in our group.

• Bringup chip in lab and see it through production.

• OP2 Emulation: Setup the flow with ethernet, Schim logic to connect ethernet IP.

• Cloud infrastructure chips. Block level verification of different blocks.

• UVM verification of a critical block, Traffic Scheduler, highly configurable, highly parametrized block, in NVMe over fabric(ethernet) chip. Functional coverage of some other blocks and GLS. Sr Member of Technical Staff @ AMD Inc. Feb 10 – Nov 11

• Verification lead for Power gating aspects of latest generation of standalone graphics and fusion products, using MVSIM, UPF, CPF. Verify PGFSM IP.

• SOC power gating verification of standalone graphics and fusion chips. Involves testplan, writing tests using C++, managing regressions including Power aware.

• GLS

Contracting @ Zoran (5), Foveon(5), Tessera Inc(3). Oct 08 – Jan 10

• Integrate architecture performance C++ simulation of Memory controller into the Specman testbench environment. Modify the driver and constraints. Modify C++ client generator to match the specman interface. Verify with DDR2 memory.

• Implement system level register tests and other tests on a LCD TV SOC.

• Develop model to emulate derivative sensor chip and verify with System verilog.

• Design USB ISO Endpoint controller for video. Architect, design and implement a proprietary Packet protocol as a backbone of communication within a system. Sr ASIC Engineer @Nvidia Inc. Apr 05 – Oct 08

• Verification of PCI Express chipset. Implement a testbench with generators, drivers, monitors, scoreboards, RefModels. Generate random constraints. GLS,

• Create an environment to test HyperTransport, IOMMU

• Integration and upgrade of USB, Ethernet MAC and SATA Designs. Sr MTS @ Rambus Inc Nov 02 - Apr 05

• Responsible for the PCI Express PCS IP microarchitecture, design, verification and Synthesis. PCS IP. GLS and FPGA implementation.

• Responsible for bring up of XAUI and Infiniband SerDes chips. ASIC Design Engineer @ 2Wire/Nazomi Inc. Mar 99 - Oct 02

• Design a small Packet processor used as a general-purpose processor for HPNA MAC control, in the SOC. Microarchitecture/Design/Verification and GLS

• Verification/Synthesis of the Java coprocessor for MIPs processor architecture.

• Setup the simulation and synthesis environment to verify. Contract @ Web TV Jan 98 – Mar 99

• Design and Verification of DES3 Decryption for WebTV/Satellite Set-top Box SOC. Setup code-coverage tool.

Design Engineer @ S3 Inc. Feb 94 - Jan 98

• Design of PCI and Burst Command Interface for the Savage 3D chip.

• Verification and GLS.

• IKOS verification PAL/NTSC Decoder. System design and board design of a Video Scalar Chip Vision/VA. Design of a TV Tuner and MPEG board.

Design/Apps Engineer @Austek Microsystem. Aug 90 - Jan 94

• Design a 3D graphics board using Austek rendering Engine. Design involved three Altera FPGA. An EISA Bus controller, DRAM controller and Video timing Generator. Presented Best of Comdex 93 by Byte Magazine.

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