Design Engineer Fpga

OBJECTIVE ASIC/FPGA design Engineer position in talented and motivated team

CORE COMPETENCIES

Electrical system, hardware, ASIC/FPGA whole life cycle development experience

Expert on ASIC/FPGA/hardware design verification tools VCS, Verdi.

Extensive telecommunication and Audio/Video, electric drive related experience.

A track record of 15 ASIC/FPGA/IP products released to market

Excellent problem solver, versatile team player and quick leaner.

Objective Oriented, focus on results

TECHNICAL SKILLS

Standards: 4G/5G,10G Ethernet, 10G SONET/OTN, GFP, T1/E1, Timing standard,

DTV/DVB/DAB, HDLC, PCI, SPI/I2C, UART, I2S, A-Phy etc.

Program Languages: C, Assemble, Verilog, System Verilog, UVM, VHDL, Perl,python, TCL .

ASIC Tools: Synopsys, Cadence, Mentor tool sets.

FPGA Tools: MODELSIM, SYPLICITY, Xilinx ISE, Xilinx VIVADO, ACTEL Libero IDE, ALDEC.

Board Design Tools: PADS, OrCAD, Allegro, PROTEL, ALTIUM, etc.

Board Debug instruments: Oscilloscope, Logic analyzer, etc.

PROFESSIONAL EXPERIENCE

Xscend Technology

ASIC design/Verification Engineer ( Sept. 2022 -Jan 2024 )

MIPI A-phy Project

MIPI A-phy Data link layer Architecture design according the standard. Data link layer block RTL coding using systemverilog. RTL LINT and CDC check. Data link layer block Verification plan development, UVM verification environment development, test case development, code coverage collection and analysis. Perform Stress test and performance test using Verdi. System level test case development and debugging.

D&V Electronics, Detroit, MI

FPGA Engineer (Aug. 2021 – Aug.2022)

Advanced Power Emulator system

High Power electronics Emulator Algorithm implementation using VHDL, verification, lab testing.RTL design and Test bench development and verify the design.

Safran Electronics and defence, Peterborough, ON

FPGA Engineer (Feb. 2021 – Aug. 2021)

Nuclear Power Plant Control System according to customer requirement

Design and Verification and lab test procedure document Development according to according to customer requirement and Do254 standard.

RTL design and Test bench development and verify the design .

Johns Hopkins University, Baltimore, MD

Hardware/FPGA Engineer (12, 2019 - 06,2020)

Da Van Ci Medical Robot Project

Medical surgery Robot arm control FPGA design. Control Algorithm implementation. Design optimization, Reorganize the Design to meet industry stand for open source purpose.FPGA/software integration and test.PCB board debug and schematic bug fix.

NOKIA, Chicago, IL

FPGA Engineer (05,2019- 09,2019)

● 4G/5G Beam forming Project

4G/5G beam forming technology research and study. Beam forming technology development strategy and FPGA architecture documentation development.

Alpha-Numero, Endicott, NY

FPGA engineer (09,2018 – 01,2019)

• Boeing 777x IFCU FPGA Verification and Validation

Verification procedure document Development according to Do254 standard.

Test Script development.

Perform FPGA lab test according to the requirement and test procedure.

MDA, Montreal

FPGA Engineer (07,2018-08,2018)

Satellite Solar Panel and Antenna control unit

Design requirement development according to customer requirement according to the Do254 procedure.Review schematic design according to system requirement.

Control loop timing calculation and detailed block design according to system requirements.RTL coding using VHDL. System schematic review.

GE Transportation, Erie, PA

Drive Control Engineer (08,2016 – 06,2018)

• Locomotive Traction Control System

Traction Control Electric Drive Motor control algorithm implementation, filter design, Traction Control Electric Drive Motor control FPGA design/debug/verification.

Traction Control diagnostic software lab test and field test, test data analysis

IGBT drive Card Issue analysis and fix. Verilog/VHDL RTL design, Xilinx ISE and VIVADO,Zynq, Matlab used.

Freelancing startup company, Chicago, IL

Senior system Engineer (02,2016 – 08,2016)

• wearable electrical system

System design, schematic capture, PCB layout, software design.

Caterpillar, Peoria, IL

FPGA Engineer (02,2015 -11,2015)

• Electric drive system Electric Drive Current leak monitoring algorithm design and verification, VHDL RTL design. Electric Drive Voltage monitoring algorithm design verification (fix point DSP), filter design, Electric Drive tri-level switching motor control system design and verification. Electric Drive tri-level Switching modulation algorithm implementation and verification. Electric drive system implementation and system testing using LabVIEW. VHDL and Xilinx ISE and VIVADO used.

Knowles Electronics, Chicago, IL

Senior system engineer (04,2014-10,2014)

• Audio process system

Microphone algorithm verification System design, schematic capture using FPGA and

microprocessor

FLEXLINK protocol IP design, verification. and implementation.

Block RTL design, simulation, synthesis, place and route, Static timing analysis.

LMI Technologies, Vancouver

FPGA/Hardware engineer (10,2012- 07,2013)

• Laser measure system

Camera control and Image processing FPGA algorithm design and implementation.

Block RTL(VHDL) design, verification, synthesis, place and route, Static timing analysis.

System design, schematic capture, PCB layout use Altium.

Hardware/software integration, debug and test.

SARANCE Technologies, Ottawa

ASIC design Engineer (03,2010- 09,2010)

● 10G Ethernet MAC and PHY

Created verification plan and developed verification environment.

RTL Behavior model development. Test case development and run simulation.

Successfully verified the 10G Ethernet MAC and PHY IP using VCS.

BTI Systems, Ottawa

Hardware Design Engineer (03.2007-01,2009)

● 10G SONET/OTN systems

Key contributor of the 10G MUXPONDER (A full FPGA based (Xilinx vertex 5) optical

communication system used to Aggregate 10 port of Giga bit Ethernet or Fiber

Channel to 10G OTN) and 10G Transponder (10G 3R system) system.

Contributed in the full FPGA (using vertex 5) based system in block level RTL design, system level simulation, verification plan creation and execution, and lab testing/debugging of the 10G Optical MUXPONDER, Contributed in the schematic capture, FPGA design and PCB bring-up, debug, performance test of the 10G Transponder system.

ZARLINK (formerly Mitel) Semiconductor, Ottawa

ASIC Design Engineer (04,2000-10,2006)

● Giga bit Ethernet Switch

Challenged by a complex and high-speed design. Designed the MAC, RXDMA, Granule manager, buffer manager, PCI interface, SPI interface in RTL.

Created verification plan and developed test cases. Successfully simulated the system using VCS.

Perform bench evaluation using high speed signal generator and scope.

● DSP/CPU based SoC Processor

Low power DSP (with FFT) based Voice Over IP processor and Voice echo canceler

(ZL38004) processor with Noise Reduction and Codec

DSP/CPU verification.

Designed and verified the peripheral MAC, TDM, SPI, I2C and voice CODEC in RTL.

Interface. Designed part of the DSP firmware. FPGA emulation using Xilinx ISE.

Contributed to the system Verification using SoC co-verification Methodology using VCS.

FPGA Prototyping test and debug

Evaluation board schematic design, Board bring-up, debug, Bench Evaluation script

Development, perform chip bench test.

● Main contributor in the Mitel/ZARLINK TDM series product (Zl50023, Zl50012,

ZL50061, M90820), responsibilities in clued:

Main contributor of the new TDM architecture which was granted a patent

Main block RTL design, simulation, synthesis, Static timing analysis.

System level simulation plan creation, test cases creation, system level Simulation with VCS.

DPLL block Simulation, FPGA Prototyping test and debug.

Clock duty cycle tolerance performance improvement.

Silicon on board evaluation and characterization.

CESOP (Circuit Emulation Service Over Packet Processor ZL50120)

Contributed to the design and verification of world's first CESOP platform.

Designed the TDM switch part with 1k backplane channel and 1k local channel.

Designed the TDM-to-packet interface block.

Created a new TDM architecture to reduce memory size and power consumption.

The creation of the BER (Bit Error Rate) IP was reused in other products.

Developed the simulation plan, created the test case and run simulation with VCS.

EDUCATION

B.Sc.: Electrical Engineering, Tsinghua University, Beijing, China

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