Data Center Project Management

John E. Del Riccio Jr.

**** ********* **, **********, ** 60540 Cell 347-***-**** ************@**********.***

SKILLS

Scheduling

Product Management

Project Management

Design Management

Budgeting

System Architecture

Resource Allocation

Docker

CPU Performance

FPGA Architecture/Design/Simulation

Kubernetes

Data Center Infrastructure

Circuit Pack Design/Simulation

Linux

CI/CD Automation

8051, 68000, 68332, 68360

Vendor Negotiation

C language

Exchange Protocols

System Verilog

VHDL

Modelsim

Questasim

Jenkins

Ethernet

People

Networking

Assembly languages

Vivado

SOC/ASIC Design

Windows

TCP/IP

Protocol design

WORK HISTORY

G-Research

Managing Director- Low Latency Engineering

Mar 2022- July 2024

Oversee eight low latency engineering groups: Market Data, Execution/Algo safety, Algorithmic Trading, FPGA/Hardware Acceleration, Networking, Exchange Normalization, Linux/Server Deployment, and DevOps. Responsible for all Data Center operations for 30 venues globally.

Prime Broker interactions where used, technology evaluation, Microwave/Satellite infrastructure, HFT applications using HW acceleration techniques, system level architecture, and HW/SW design methodology.

Microsoft

Principle Engineering Manager

June 2020 – Mar 2022

Oversee Azure Cloud software/hardware acceleration development for Networking, Storage, and Cryptography functions for more efficient usage of CPU core allocation. Manage all UVM and HW validation for cloud based infrastructure.

Wolverine Trading

Principle

Director of Engineering

March 2019 - June 2020

October 2015 - March 2019

Oversee a group of 35 staff members including 5 managers (FPGA design, Board design, UVM, Networking, Embedded SW, Application SW, System test, DevOps) focusing on implementing various trading strategies that cover multiple exchanges and applications. Responsibilities include end to end product/project management, budgeting, resource allocation, architecture and design of trading systems, real time evaluation of those engines, exchange connectivity optimization, ultra low latency Hardware Acceleration techniques with data compression, IP management, vendor management, and Hardware-Software Interface specifications for platform development. Complete Responsibility for end to end development and management of product life cycles.

Lead FPGA Architect

October 2014 – October 2015

Architected innovative FPGA-based Trading Engines, managed hardware development, software development, verification, documentation, vendor management, system integration and optimization, RTL coding and embedded C software.

Teradyne

Hardware Engineering Manager

March 2014 – October 2014

Oversee a group of 10 Digital designers (FPGA & Board) across three locations along with a team of embedded software engineers for Silicon Test Equipment.

Citadel Securities

Lead FPGA Architect HFT

November 2012 – January 2014

Lead FPGA Architect for High Frequency Trade applications: PROPRIETARY

UBS

Director

August 2011 – November 2012

Hardware Architect for a Low Latency Trading Platform using FPGA’s as a Hardware Acceleration Engine. Market Data vendor evaluation, FIX Acceleration, Risk Check Engine, Full Ordered Multicast HW processing.

Qualcomm

Team Lead

July 2006 – August 2011

Architected and designed an ALTERA ARIA FPGA to act as a remote server download manager to configure other FPGA’s on emulation platform. Wrote embedded C code running on NIOS II MicroControler to provision various interfaces and performed board level diagnostics.

Architected and designed an ALTERA Stratix IV FPGA with over 800 I/O to verify the integrity of an ASIC intended to be implemented in a mobile handset. Several circuits ran at 480 Mhz and the design had integrated several pieces of IP including Triple-Speed MAC, NIOS II, and SSBI Controllers. This design and integration required managing a team of three engineers on other designs associated with the platform.

Architected the implementation of an Integrated a Synopsys Ethernet MAC Core into an ASIC to be implemented in a mobile Handset. This effort required complete provisioning of all core options, vendor management, and verification coverage which was performed in India.

Architected Altera GX FPGA running at 500 Mhz that interfaced a Signal Processing unit to a mobile Test Set. Managed the designers for the FPGA & circuit board.

Lead Engineer responsible for Architecting ALTERA GX FPGA that interfaced to a CPRI based Radio-Head to a Base Station.

Lead Engineer responsible for Architecting and designing an Altera GX FPGA that interfaced the baseband interfaced of a Radio Module to a SRIO backplane. This FPGA contained several pieces of IP including a NIOS II MicroController, SRIO Core, GigE Core, and I2C Controller. I was also the lead engineer on system integration.

Design of a Xilinx Virtex IV FPGA to bridge Communication between a TI DSP Complex and Integrated DDC/DUC device. A bus model was required to be developed for the DSP for verification purposes.

TYCO (MA/COM)

Principle Digital Design Engineer

2002 - July 2006

Architected Designed a telemetry interface for a defense application to track projectiles implemented first in a in a Virtex IV FPGA and subsequently in an ASIC.

Architected and designed an Interpolating Algorithm for closed loop non-linear correction of Digital Power Amplifier. Led the entire development of the Virtex IV FPGA which included 3 other engineers.

Developed algorithm for running CORDIC’s in parallel to achieve desired system performance and implemented the design in a Virtex FPGA. A patent was awarded for this design.

Lead Engineer responsible for architecting all FPGA designs, managing those designs at the implementation and simulation level, and participating in the time critical debug. This assignment included significant mentorship of junior engineers.

Lead Engineer defining FPGA Architecture for Baseband Processing Virtex FPGA and Evaluation Platform.

Design Virtex FPGA responsible for integrating signal processing ASIC design as well as all support logic required for overall functionality within Evaluation Platform.

Design of SPARTAN FPGA for interstitial module bridging Baseband Processing Module & Analog Loop Module for Phase modulator prototype.

Tellium Systems

Senior Hardware Engineer

2000- 2002

Design of VIRTEX FPGA for control of Switch Module.

Architected and designed DSP Cluster Processing Core.

Design of SPARTAN FPGA interfacing DSP Cluster to MEMS

Design of Quad 2.5G Module for Optical Cross Connect including MPC860 Processor subsystem

Lucent Technologies (AT&T Bell Laboratories)

Member of Technical Staff

1987-2000

Lead Hardware designer on SPU Module for ONE CELL

Lead Hardware designer of Base Band Unit in charge of FPGA

Architecture and all Signal Processing Interfaces as well as leading all board level & chip level simulations.

Mentoring several younger designers on the project.

Re-Designed FPGA on DRM (MicrCell) and added Analog Air Interface feature due to several existing design flaws inherited from previous implementations.

Hardware Architecture of Base Band Unit

Lead Hardware designer of Base Band Unit including both board & FPGA design, and MPC860 design.

Lead Engineer for Board Level Simulation Activities

Mentoring of the younger more inexperienced designers

Hardware Architecture for ADSL Multiplexer

Design of Backplane Interface FPGA for ADSL Multiplexer

Design of FPGA to interface ATMIZER to memory subsystem.

Design of Backplane Interface Subsystem for

BNS-2000 Communications Switch; Included

Transmit & Receive FPGA’s

Design of Microprocessor based Ethernet Interface Circuit

Pack for use in the Datakit II: Included Shared Memory and Backplane Interface FPGA’s.

Design of Queue Server and Group Address Replicator FPGA’s for TRUNK-ATM.

AT&T Bell Laboratories

Senior Technical Associate

1987 - 1992

TRUNK-T3/AI-T1 BNS-2000 CPU assist FPGA’s.

SMDS ChipSet Prototype Board Design and SMDS 802.6 Chip Set Design.

AU45 SMDS Trial System FPGA Design.

FPC Prototype Board, Fiber Protocol FPGA’s for BNS2000 CIM Module

EDUCATION

New Jersey Institute of Technology

MS Computer Engineering 1996, 3.5 GPA.

BS Computer Engineering 1995, 3.75 GPA

DeVry Technical Institute AS EET, 1987, 4.0 GPA, Faculty Asst.

INTERESTS

Music, Drums, Boating, Sports, Horses, Exercise, Capital markets

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