Firmware architect, engineer.

Andy Hoffman

Las Vegas, NV • ****.*******@*******.*** • 323-***-****

www.linkedin.com/in/andy-hoffman-1aaa783

Please note that I am open only to local or remote job opportunities. BACKGROUND AND INTERESTS

My background and expertise are in architecture, design and development at the software/hardware boundary. I created or co-created multiple innovations that became industry standards, authored multiple patents in USA and EU. I am keen on conceiving and building proof-of concept prototypes, validating, documenting, and working with production teams on implementing it into products.

I have a background in electronics design, which allows me to effectively collaborate with hardware engineering, including electrical, power, thermal. I often receive feedback from my peers, mentees that I’m the “go-to guy” for questions and issues around complexities and ambiguities. I believe I have talent explaining concepts, coaching, presenting ideas. EXPERIENCE

Senior Software Engineer, ASML, Wilton CT; Aug 2022 – May 2024 Firmware design and development for opto-mechanical mechatronics for next-gen EUV lithography. Architected and implemented firmware interacting with hardware, optimizing performance, facilitating calibration and diagnostics. Reason for leaving: Relocated for personal reasons. Principal Engineer, Western Digital Corporation, Phoenix AZ; Oct 2018 – Mar 2021 Architecture and development of firmware for next generation performance enterprise SSD/NVMe storage products. Architected and implemented software/API stacks for new hardware, in multi-CPU and multithreaded parts of firmware, exhaustive functional and stress testing, proving functional correctness of the HW/FW stacks and benchmarking its performance. Saved the company substantial money, time, and customer satisfaction, by discovering several hardware issues, preventing it from making to the silicon.

Embedded Systems Engineering, Raytheon, Tucson AZ; Jul – Oct 2018 Architecture and Development of RT-critical software for Missile Systems. Integration of Data Distribution Service (DDS) standards into Weapon Open Systems Architecture (WOSA). Reason for leaving: I was required to eventually renounce my EU citizenship, which I wasn’t willing to do. Senior Staff Software Engineer, Intel Corporation; 1999 – 2018 Conceptualized, architected, designed, developed the technologies and projects:

CPU/FPGA integration: Led performance, power and thermal management architecture and development for Intel first CPU/FPGA integrated system. See technology info at: itpeernetwork.intel.com/intel-processors-fpga-better-together.

HPC (High Performance Computing, a.k.a. Supercomputing): Developed numerous technologies for enhancing and optimizing performance and energy efficiency. Authored numerous patents. Paper: ieeexplore.ieee.org/document/7016384.

HWPM (Hardware Power Management, a.k.a. Intel® Speed Shift Technology): It allows optimized performance vs. power management w/o OS support (much slower and typically outdated). I have received several Intel recognitions and awards for this invention. See description of the technology at: software.intel.com/en-us/articles/intel-xeon-processor-scalable-family-technical-overview.

BMC/IPMI: New types of platform telemetry: Volumetric Airflow and Outlet Temperature sensors. These features are indispensable today for power/thermal/density management from rack- to datacenter-levels in Cloud and HPC industry. See: OpenStack Nova documentation and paper: ieeexplore.ieee.org/document/6526836.

NM (Node Manager): NM is present on all Intel servers now and is an indispensable feature of power, performance and thermal management, from individual system, through rack, to datacenter levels in Cloud and HPC business. See Intel video: https://www.youtube.com/watch?v=bY5qR2GPAiU, and OpenStack article: https://wiki.openstack.org/wiki/User_talk:Fengqian

FSC (Fan Speed Control): I re-architected and re-wrote from scratch and single-handedly the FSC on Linux for BMC (Baseboard Management Controller). Prior, BMC used antiquated RTOS and undocumented code. See ‘Fan’ sections in standard IPMI specification. My code is the base for FSC in Intel servers.

UEFI: Technical team lead for Intel server BIOS development with early EFI. Contributed to EFI/UEFI/Tiano architecture in the following areas: HII (Human Interface Infrastructure), Setup, Data Hub, microcode update, CPU and PCI driver stacks and few others. My code and technical writings became part of UEFI codebase and documentation.

Itanium: Lead BIOS development team for the first-ever Itanium/Merced platform. It was a workstation, codenamed “Big Sur”. The BIOS codenamed “Kitty Hawk” was a novel pre-UEFI BIOS re-write in C.

Lab: Parallel to my projects, I lead the lab for my team, supervising and instructing technician staff. Developed automation, dispatchers for unattended benchmarking (e.g., LINPACK/SPECpower/web/jbb), hardware and software methodologies and instrumentation for telemetry, parsers and analyses for experimental runs, scripts and templates for analytics. Managed equipment and material budgeting and procurement decisions. Member of Technical Staff (MTS), Lucent Technologies, Bell Labs, Optical Networking Group Architecture, design and development of reliability critical RT software/firmware for large Sonet/SDH cross-connect telecommunication switches on VxWorks RTOS running on Motorola embedded controllers, implementing high redundancy, health detection and failover mechanisms.

See product info for DACS II & WaveStar DACS: http://www.onlineauthoring.com/WritingSamples/PDFs/4F_10G.pdf. Hardware & Software Engineer, Test and Measurement Systems Inc. (HP Channel Partner) Designed and developed PCI controllers for HP/Agilent Instrument Control stack. I have developed a product in its entirety, including hardware, FPGA, RTL, surrounding discrete electronics, software, GUI, drivers and libs for VEE/SICL for UNIX/HP-UX & Windows. See the product (p/n: TAMS xx622): http://www.techsoft.de/documents/tams_62622.html. KEYWORDS

OOD/OOP, C/C++, Python, shells, Perl, embedded, bare-metal, RT OSes, Linux, VxWorks, Windows, firmware, drivers, BIOS, VB, SQL, ODBC, ORM; MPI, FEA, PID, UML, Agile, Git, Gerrit, CI/CD, Jenkins. Math, timing, power, sequencing, structuring data, logic, algorithms, parallelism, multi-threading, event-driven design, race conditions, deadlocks.

Mechatronics, electronics, hardware control and monitoring, performance, power, performance/watt, thermal management, at silicon, platform, system and rack levels.

Use cases, solution conceptualization, requirements, methodologies, high- and low-level designs, writing specs, presentations, reviews with peers, stakeholders, data gathering and analysis, guides for internal references and customer documentation. Familiarity with RF. Exposure to AI. Office and collaboration tools, Word, Power Point, Visio, Excel’s Visual Basic for data analysis. EDUCATION

MS Computer Science

MS Electrical Engineering

Silesian University of Technology

OTHER

Citizenships: USA & EU.

Please note that I am not willing to renounce my EU citizenship, which means I am ineligible for security clearance. References provided once mutual interest is established.

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