Firmware Engineer

Anshumaan Bollampally Reddy

Ph: 303-***-**** Email: ***********@*****.***

Address: **** * ***** ******, **********, CO 80023

PROFESSIONAL SUMMARY

Dedicated firmware engineer with 4+ years of experience in Electrical and Computer Engineering. Specialized in firmware programming, digital hardware design, verification, and digital signal processing, with a proven track record in driving business success through the strategic application of cutting-edge technology solutions, committing to deliver technical excellence, and fostering innovation to meet evolving market demands.

TECHNICAL SKILLS

●Languages: C/C++, MATLAB, Python, and Verilog/VHDL

●Tools: Experienced with Microsoft Word, Excel, PowerPoint, Visual C++, ModelSim, Altera Quartus, Linux/Emacs/GNU, Docker

●Platforms: Microsoft Visual Studio, Google Test Suite, Microsemi Flashtec NVMe3016 Flash Controller

●Methodologies: Git, JIRA, Agile Methodology

●Other: Hands-on experience in Soldering/Bread Boarding, Electrical Lab Tool Usage

EDUCATION

●Master of Science in Electrical Engineering (August 2023 - Present)

University of Colorado, Boulder (Coursera)

Focus on Embedded Firmware and Hardware Design (FPGA/ASIC)

●Bachelor of Science in Electrical and Computer Engineering (August 2015 - December 2019)

University of Colorado, Boulder

Focus on Digital Signal Processing/Digital Filters, Embedded Programming Labs, Linear Algebra, Probability, Digital Logic/Verilog Hardware Design/FPGA, Circuits as Systems, Linear Systems, and Computer Architecture (RISC-V w/ Codasip)

PROFESSIONAL EXPERIENCE

Firmware Engineer, Intel/Solidigm (January 2021 – December 2023)

●Spearheaded daily triage for continuous integration (CI) to ensure the optimal health of drives, utilizing JIRA for meticulous issue categorization and publication of comprehensive daily reports, thereby enhancing operational efficiency, and minimizing downtime.

●Pioneered firmware updates for drives, rigorously verifying enhancements through unit tests in Visual Studio on Concordia simulator, resulting in improved performance and reliability, ultimately enhancing product competitiveness.

●Improved firmware to support multiple namespaces for NVMe drives, expanding functionalities to meet evolving market demands, thereby driving revenue growth and market share.

●Fostered collaborative relationships with firmware stakeholders to validate DMA functionality through strategic utilization of serial port commands and Google Test Suite framework, resulting in faster time-to-market for new products and features.

●Demonstrated a commitment to continuous learning by studying the Microsemi Flashtec NVMe3016 Flash Controller, enhancing firmware development capabilities and contributing to ongoing innovation initiatives that directly impact business operations.

●Developed robust test suites for cascaded message routines, driving efficiency and reliability in firmware operations, while contributing to the creation of address library routines leveraging DMA firmware, resulting in improved product quality and reduced time-to-market by 6 months.

●Leveraged Docker for streamlined development tasks and adopted best practices in code repository management through proficient use of Git, JIRA, and Agile Methodology, optimizing development processes and enhancing collaboration efficiency.

●Executed debugging with GreenHills debugger (GHS) and Intel diagnostic framework.

Junior Engineer, CNEX Labs (February 2020 – May 2020)

●Mastered distributed repository management using TortoiseGit, optimizing collaboration and version control for streamlined development processes, resulting in faster project delivery and improved product quality.

●Engineered efficient code deployment strategies using IAR for serial port prompt translation, thereby reducing development cycle time and improving time-to-market by 3 months.

●Conducted comprehensive testing of NVMe commands, ensuring firmware functionality alignment with performance expectations and industry standards, enhancing product reliability and customer satisfaction, which resulted in a 50% drop in field-reported bugs.

●Generated insightful test reports for security software on flash drives, providing critical insights for performance optimization and product enhancement initiatives, ultimately improving product competitiveness which resulted in a 20% I/O improvement in performance.

Intern, Seagate Technology (June 2018 – December 2019)

●Acquired proficiency in the build environment, utilizing Perforce and Code Collaborator for efficient code development and collaboration.

●Leveraged the Lauterbach emulator for robust debugging, ensuring the integrity and reliability of firmware operations in real-world applications.

●Optimized the Defect Description Table (DDT) to minimize DRAM consumption, enhancing operational efficiency and reducing resource overhead, which allowed a 10% improvement in the size of the DDT.

●Implemented critical fixes and additions to SMART frames, enhancing functionality and performance in alignment with evolving market demands.

Contact this candidate