Analog IC Design

Yuanqi Guo

*** ***, **** *. **** St., Urbana, IL, 61801, USA

********@********.*** • 734-***-**** • LinkedIn profile Summary Statement: Dedicated and innovative graduate student in Electrical and Computer Engineering with hands-on experience in tape-out processes and industry-standard EDA tools. My background features extensive research in analog design, specializing in advanced MOSFET and FinFET technologies, including 5nm and 16nm process nodes. I am eager to apply my skills to drive cutting-edge advancements in the semiconductor industry. EDUCATION

University of Illinois Urbana-Champaign (UIUC), Champaign, IL, USA Aug 2022 – Dec 2024 M.S. in Electrical and Computer Engineering

Research Assistant, focus of research: High-speed wireline transceivers, SerDes. Coursework: Advanced Analog Integrated Circuits, SoC Design, Signal Integrity, Broadband Wireline Circuits, VLSI, Advanced Device Physics, Machine Learning, RF & mm-Wave Design; Teaching Assistant for VLSI Design (fall 2024) University of Michigan (UM), Ann Arbor, MI, USA Sep 2020 – Apr 2022 B.S. in Electrical Engineering

Coursework: Analog Integrated Circuits, VLSI Design, ADC, Computer Architecture, Integrated Microsystems Laboratory, Embedded Control System, Semiconductor Devices, Wireless Communication; Teaching Assistant for the ECE core course on Analog Circuit (winter 2021)

Shanghai Jiao Tong University (SJTU), Shanghai, China Sep 2018 – Aug 2022 B.Eng. in Electrical and Computer Engineering, Minor in Entrepreneurship Coursework: Analog Circuits, Logic Design, Programming and Data Structures, Honors Calculus, Honors Physics; Teaching Assistant for Fundamental Chemistry and Chemistry Laboratory; Dual degree program of UM-SJTU Joint Institute SKILLS

Software: Lab Equipment: Programming and Systems:

Cadence Virtuoso, Spectre, Spice,

DRC/LVS/QRC, ADS, HFSS, CST,

MATLAB & Simulink, PCB Design tools

Oscilloscopes, SMU, TLP system,

VNA, Signal/Spectral Analyzer,

PCB assembly tools

C++, C, Verilog, Python,

MATLAB, LaTeX, Microsoft

office tools, Windows, Linux

INTERNSHIP

Student Technical Intern (IO/ESD) NXP Semiconductors, Austin, TX May–Aug 2024 & May–Aug 2023

• Performed snapback modeling of 3-stacked MOSFET stages which verified both 3.3V output driver and power clamp circuits behavior under electrostatic discharge conditions; Contributed to the analysis of potential substitution of on-chip clamps with imx95 package capacitors (24 Summer).

• Delivered key results from ESD simulation and TLP characterization projects that contributed to the success of NXP's S32K5xx IO library. Collaborated closely with the ESD team and presented findings on the CDM robustness of a 2-stacked power rail clamp network in an industrial 16nm FinFET process (23 Summer). PROJECT EXPERIENCE

Integrated Circuits Research Group UIUC Aug 2022 – Present Graduate Research Assistant Advisor: Prof. Elyse Rosenbaum

• Acquired extensive experience with IC tape-out and silicon testing for advanced MOSFET and FinFET technologies.

• Gained hands-on experience in designing mixed-signal circuits including ADCs, DACs, RX, TX, PLLs, filters, CTLEs, regulators and other analog components.

• Led the design and tape-out of an on-chip oscilloscope, encompassing both analog design and digital synthesis. Laboratory of Ultrafast Integrated Systems SJTU Apr 2021 – Jan 2022 Undergraduate Research Assistant Advisor: Prof. Xuyang Lu

• Proposed an RF radar working at 300GHz to detect the locations and measure the rotational speeds of multiple spinning objects by exploring the use of frequency diverse array.

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