Hardware Engineer

John Joseph Carrillo

San Jose, California *****

Qualifications Summary:

Dedicated and results-driven Lead Hardware Engineer with expertise in PCB Design, PCIe, ASIC/SOC devices, Verilog RTL, FPGA Design, Encoding, Debugging, and Emulation.

Experience with High-speed design and system architecture, Serial interconnect ethernet protocols and ethernet optical interfaces, Networking and networking protocaols, Hardware validation and verification, Hardware emulation and software simulation.

Strong troubleshooting skills, capable of identifying and resolving hardware issues using various debugging tools and techniques. Python, C++ programming and shell script for automated testing. Lab environment verification testing.

Lead PCB design and specification engineer, High Speed SERDES for ethernet simulation, debug SERDES PCIe related issues including IP’s, Cadence Concept/Allegro PCB implementation, Cadence Palladium and Protium hardware emulation, documents design, and schematic review and analysis. Google docs and spreadsheets. Hardware Validation Engineer

Groq San Jose, CA Apr 2024 – Sept 2024

Hardware validation engineer for Groq blade product, code-named Axolotl, that encompasses four TSP chips and dual Altera Agilex FPGAs for ethernet host communication and an Octeon processor for control and a STM processor for maintenance. Performed hardware validation on blade and AXL-chassis incorporating 8 blades with fans and power supplies. Cadence Concept/Allegro PCB schematic/layout review and design. Python, C++ and shell scripting for test of high-speed serial chip-to-chip interconnects and ethernet host connections. Lab environment and server room testing. Linux based software debug.

Validation Emulation Engineer

Meta Sunnyvale, CA Apr 2023 – April 2024

Emulation engineer for Cadence Palladium and Protium hardware emulator products used for hardware emulation of SOC RTL design for computational acceleration devices for artificial intelligence and machine learning applications incorporating CPU, memory, and switching IP. Cadence Speedbridge and EDKs for real-time I/O simulation of ethernet, PCIe,and USB interfaces. Python, C++ and shell scripting for test. Test Development and Validation Engineer

Nvidia Santa Clara, CA May 2022 – Mar 2023

Test engineer for GPU SOCs used for computational acceleration for artificial intelligence and machine learning applications incorporating proprietary serial switching and CPU IP along with GPU in SOC. PCB schematic review and design. Python. C++ and shell scripting for test development. System administration of lab PCs for Linux OS upgrades. Hardware Development Engineer

Cisco Systems San Jose, CA Jun 2021 – Apr 2022

Network interface modules for hardware security platform supporting optical SFP+ and RJ45 copper interconnects. Design, bring-up and test working with diagnostic software and software OS teams. FPGA RTL verilog design, PCB schematic review and design. Network switch product. JTAG and I2C verification and testing. JIRA tracking and similar software for issue tracking.

Hardware Development Engineer

Cisco Systems Milpitas, CA Dec 2019 – Dec 2020

Three generations of switching/router products Azteca+, Questra, and Blackbolt doing unit testing focused on system clock distribution, data eye captures between devices, power distribution and sequencing.

Test validation and bringup of first article systems. Cadence PCB schematic and Allegro layout review and analysis of linecards and integrated routing/switching system. Lab environment testing. JTAG and I2C verification testing. Sustaining Hardware NPI Engineer

Juniper Networks Sunnyvale, CA Jun 2016 – Nov 2019

Hardware engineer working closely with manufacturing test and ODMs on field failures and EOL issues on released products, NPI products EDVT, and root cause analysis of field failures. Salesforce and similar customer tracking software.,Investigation of RMA customer returns to determine cause of failures, design issues and manufacturing defects.

Network switching chassis systems with multiple linecards/routing processors and fixed integrated systems. Ixia tester/generator for NPI validation of large rack system with multiple optical linecards with daisy chain fiber connections in large walk-in thermal chamber.

PCB schematic and layout review and design. Cadence Concept schematic capture and Allegro board layout. Hardware Development Engineer

Cisco Systems Inc San Jose, CA Jan 2011 – May 2016

Design of manufacturing test platforms for bring-up and manufacturing test for high end core router products fabric cards, route processor cards, backplane loopbacks of high-speed SERDES. Lab environment verification testing.

RTL Design review and initial bring-up of production boards and failures in high-volume production.

PCB schematic and layout review and design. Cadence schematic and Allegro board layout. Hardware Engineer

Sigma Designs Santa Clara, CA July 2010 – Dec 2010

Consultant on Xilinx FPGA design for hardware emulation of ASIC design. Dual FPGAs for MAC and PHY functions with high speed SerDes for transmitting modulated RF data to PHY chip. Hardware Engineer

Opnext Los Gatos, CA Jun 2009 – Jun 2010

Sustaining engineering of optical transceiver product for 40G duobinary and DPSK modules, including TI DSP, 860 PPC, and multiple Xilinx FPGAs. OrCAD, Allegro, ISE toolset.

Debugged SFI-4 and SFI-5 interconnects between MUX and Framer devices.

Debug FPGA problem related to SFI-4 alignment state machine. Hardware Engineer

Finisar Corporation Sunnyvale, CA May 2008 – May 2009

Board level design of optical module for 100Gb CFP modules including 10x10Gb interface using x1 TOSA and x4 ROSA modules.

PCB stackup and escape patterns from high-density BGA optical modules and the module straddle-mount edge connector.

Hardware Test Development Engineer

Micron Technology San Jose, CA Jan 2008 – Apr 2008

Design test boards for image sensor camera devices using PC-based test system with Altera and Xilinx FPGAs using ISE, Quartus, OrCAD, PCAD, and Allegro.

Hardware Development Engineer

IDT San Jose, CA Jul 2005 – Dec 2007

Validation and evaluation boards for networking devices including PCIe switches with hotswap and sleep mode power management.

Test boards were used to verify functionality of PCIe GEN 1 and GEN2 devices and reference designs for customer applications.

Serial RapidIO, network offload TCAM routing, and high-speed serial XAUI interfaces. Hardware Test Development Engineer

Intel Corporation Santa Clara, CA Jan 2004 – Jun 2005

Validation platforms for first silicon of new server chipsets for dual Xeon processors, including high- speed FSB, two FBDIMM memory channels, and PCI southbridge interface. Cadence Viewlogic, Verilog validation board for processors, chipset, and FBDIMM memory.

Board bring-up and debug of server validation platform with multiple processors, memory channels, and PCI interfaces.

Hardware Development Engineer

Hewlett Packard Cupertino, CA Jan 2002 – Dec 2003

Developed fault tolerant dual Itanium2 processor board using the Intel 870 chipset for large Tandem database system with 48VDC power distribution.

Staff Hardware Engineer

Sun Microsystems Menlo Park, CA July 1995 – Dec 2001

Designed custom memory module for the Sunfire servers mid-range and high-end products.

Awarded patents for memory module design.

Represented Sun at JEDEC standards body meetings for new memory architectures. Hardware Manager

HAL Computer Systems Campbell,CA Jan 1992 – Jun 1995

Led memory subsystem development team for SPARC based workstation product.

Designed memory control ASICs components for motherboard and memory card for 64-bit SPARC workstation. Full system level simulation, full scan implementation, BIST implementation. Education

Santa Clara University, California, United States MBA, Business Management 1982 – 1986

University of California - Los Angeles, California, United States Bachelors, Engineering 1968 – 1972

Contact this candidate