Level Data Integrity

JAGANNATHAN RADHAKRISHNAN 408-***-**** (M)

Santa Clara, CA *******@*****.*** https://www.linkedin.com/in/jagannathan-radhakrishnan-4210473

Result oriented Team Player with 10+ years of experience in SOC verification and 7+ years of design experience.

SUMMARY OF QUALIFICATIONS

●15 years of Verification experience for verifying modules, subsystems and SoC.

●7 years of design experience in the Telecom industry

●Developed VIPs for Storage (AHCI/SATA/eMMC & NVME/SOP/PQI over PCIe) standards & SRIOV

●Developed UVM TB for ONFI/TOGGLE NAND I/F standards & worked on SLC/MLC and TLC NANDs

PROFESSIONAL SKILLS

●UVM and VMM methodologies

●Low power verification methodologies (CPF and UPF)

●System verilog RTL coding

●Familiarity with Lauterbach for ARM based SoC bringup/debugging

PROFESSIONAL EXPERIENCE

AEVA (06/2022 - till date)

DV Engineer/SoC DV Lead

Responsible for SoC level test plan/execution, Emulation & Silicon bringup

●Created and maintained C/SoC Env. for LiDAR Sensor ASIC TB

●Developed UVM infrastructure for multiple ARM image loading at TB with ECC feature

●Developed common Makefile flow across SoC Sim./Emulation and Silicon validation platform

●Responsible for Full E2E data flow test Scoreboard & UVM sequence development

●Responsible for verification of all the boot stages of CMRT (Crypto Manager Root of Trust) for Secure boot functionality (FBOOT, SBOOT, MiddleWare and Thirdboot)

●Developed SV I/F based randomization support at SoC level TB

●Developed SV I/F based infrastructure to model C - printf in simulation (Very useful for C test debugging as against TARMAC based debugging)

●Responsible for Emulation bring up of full chip level data flow test sequence

●Developed SV Scoreboard for SA mode Emulation (Simulation accelerated mode) to reduce the load on Application CPU to do data integrity check

●Responsible for LPDDR4 I/F, DMA controller and A78 (ARM Application CPU subsystem) & R5 bring up for first Silicon in the lab

●Developed startup scripts in Lauterbach for ASIC bring up

●Worked with S/W and Reliability team for DDR failure analysis and root causing the issue at high temperature Env. chamber testing

●Led SoC DV team (US and India)

Facebook - as a contractor (05/2020 - 05/2022)

DV Engineer

Responsible for creating UVM TB for verification of Central Memory Controller (One of the

sub blocks of Graphics IP (Time warp Engine) as part of the Oculus AR/VR team)

●Created, and maintained the UVM verification env for Compression and Decompression block for pixel storage (with Memory management)

●Developed the Scoreboard/Ref.model for verifying the Virtual memory manager & Joint color mode (image compression based on PCA as used in ML applications)

●Created sequences, test cases, functional coverage model & responsible for closing the coverage

SanDisk/WDC (04/2017 – 05/2020)

DV Engineer (SSD controller)

Responsible for creating UVM TB for verification of Flash Translation Layer SoC

●Created and maintained the test plan for subsystem & SoC level

●Created the UVM verification env from scratch (Reference model, scoreboard & UVM sequences)

●Mentor & train the DV engineers (Domain knowledge & methodology to follow)

●Coordinated with F/W team for using microsequences at DV environment

NXP Semiconductors (08/2016 – 03/2017)

DV Engineer (IoT/Security/Low Power Microcontrollers)

Responsible for design updates of cache controller & verification at block level & full chip level. Owned UVM based IP level as well as full chip verification environment to verify Cache controller

●Implemented adaptive replacement policy in the cache controller for performance improvement

●Implemented & Integrated PRINCE on the Fly Encryption & Decryption mechanism & Verified at full chip level (For code security)

●Integrated and verified low cost AES engine at full chip level

SK Hynix Memory Solutions (06/2013 – 07/2016)

DV Engineer (Performance simulation, NAND die model & SATA Host subsystem env)

Responsible for creating the verification environment of the SSD controller. Owned UVM based Host subsystem verification environment & NAND die model for SLC/MLC and TLC NANDs.

●Implemented UVM based subsystem verification env. from scratch for SATA and ATA power management function verification & error injection and recovery handling mechanism.

●Implemented NAND die model (SystemVerilog) (Functional, timing check and command sequence check)

●Worked on test firmware in C++ and Systemverilog for measuring H/W performance

●Worked on LPDDR3/4 block verification in UVM & helped to port to full chip verification.

●Created UVM based block level verification env. For Command Q and DMA I/F of FTL

●Created UVM verification environment for verifying UPF based low power design

Link-a-Media Devices corporation, (10/2009 - 05/2013)

Santa Clara, CA (Acquired by SK Hynix)

DV Engineer

Responsible for building VMM based verification environment for NVME/SOP/PQI/AHCI & Co-ordinated with OEMs for Host F/W development (SOP/PQI), verification env for HDD Hybrid controller

●Built the verification env for host subsystem & Implemented SRIOV protocol

●Created verification environment for CPF based low power design (EMMC Controller)

●Responsible for Register Level F/W function development

●Verified DDR2 Slave I/F for caching HDD traffic

●Co-ordinated with TOSHIBA for the entire duration of ASIC development

●Created data path scoreboard for verifying AES engine

●Responsible for GATE level simulation/Functional coverage

ALTIERRE Corporation (06/2008 – 04/2009)

Staff Engineer, Access point development

Responsible for design of next generation Access point for dynamic pricing solution, based on proprietary wireless technology, targeted on Xilinx FPGA

●Worked on proprietary protocol based low power design methodology for wireless based ESL.

●Micro architecture and RTL Implementation of TDMA based Scheduler for the wireless access point

Advanced Micro Devices Inc. (06/2007 – 05/2008)

Staff Design Engineer, Memory controller verification

(CPU/GPU and Chipset Design and Development)

Verification of DDR3/GDDR4/5 memory controller using System Verilog.

EXAR Corporation. (06/2000 – 06/2007)

Staff Design Engineer, Design & verification of Telecom ASICs

(Design of Telcom ASICs – PHY and Layer1 chips)

●Design and Development of scalable VCAT/LCAS IP Core for Ethernet Over Sonet and Ethernet Over PDH series of products for telecommunication networks.

●Design and Development of SPI-4 Link Interface for OC192 Mapper / Demapper.

Education:

●MSEE (VLSI Design, DSP and Computer architecture) (San Francisco Bay University, Fremont, CA)

●AMIE (Associate Member of Institution of Engineers, Kolkata, India) in Electronics & Communication Engineering

ACHIEVEMENTS

●Implemented a protocol-based solution for achieving 5-year battery life for the wireless based Electronic Shelf Label, which has gained the retail market segment significantly.

●Successfully taped out multiple chips.

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