Software developer C++

Madan M. Das, PhD Computer Engineering US Citizen

San Jose, CA 95135 408-***-**** ********@*****.*** linkedin.com/in/madan-das-07848b8

QUALIFICATIONS FOR DEVELOPER / MANAGER

Experienced C/C++ developer in chip design, parallel processing and other areas

Demonstrated expertise in software development in algorithms & performance tuning

Great communication and collaboration skills

Excellent problem solving skills – both technical and non-technical

Extensive experience in software and flow specification, architecture, design, development & testing

Proven track record of successful projects from inception to closure in close collaboration with customers & internal teams.

Developed, trained & led high performing development teams.

Leverages technical tools, along with problem-solving and analytical skills to provide process improvements that enhance efficiency, improve product performance and achieve organizational goals.

Fast learner to adapt to new knowledge domains & contribute in its success

UL certified functional safety expert

AREAS OF EXPERTISE

Algorithms Data Structures Performance Optimization Usability Analytical Skills C++ C Python Semiconductors EDA SystemVerilog Agile Methodology AI-ML techniques Parallel processing PHP MySQL Web Development

EXPERIENCE

Mentor Graphics (Siemens), Fremont, CA USA 10/2013 – 04/2024

Principal Engineer – Design Verification (Functional Safety)

Designed and developed a new distributed concurrent fault simulator along with the underlying simulator

Improved performance by many orders of magnitude; made tremendous usability improvements

Worked with customers to set up verification environments and software to meet their verification goals and debug issues

Specified, designed and developed many core algorithms and data structures of the safety analysis products and customer enhancements

Architected and designed several key features in the clock domain and reset domain analysis, including formal verification of CDC and RDC protocols.

Worked on performance improvement of existing infrastructure using more efficient algorithms & data structures, as well as multi-threading.

Used C, C++ & python to develop. UVM, System C, System Verilog for verification and simulation.

Xilinx Corporation (AMD), San Jose, CA USA 05/2011 – 10/2013

Sr. Staff Software Engineer

Developed intelligent clock gating and other power saving techniques to reduce dynamic and static power in FPGAs.

Worked with teams spread across the globe for development, test and deployment of power saving features using formal techniques.

Used C++ for development and Xilinx simulation tools.

Apache Design Solution (Ansys Inc.), San Jose, CA USA 05/2008 – 05/2011

Sr. Principal Engineer

Developed hierarchical voltage drop analysis of SoCs for the award winning RedHawk software to cope with the challenges posed by multi-billion node circuit simulation.

Used C & C++ for development. Ran voltage drop simulations.

Cadence Design Systems Inc., San Jose, CA USA 01/2006 – 05/2008

Sr. Member of Consulting Staff

Architected the Conformal Low Power Solution for structurally and formally verifying the low power aspects of designs employing power shut off and voltage scaling techniques using CPF and UPF.

Drastically improved product performance, quality and usability by using innovative techniques, which resulted in receiving the Cadence Product of the year Award in 2006 and rapid market adoption.

Used C++ for development.

Axis Systems (later Verisity, then Cadence), Sunnyvale CA 04/2000 - 12/2005

Senior Software Engineer

Developed software for mapping customer designs into hundreds of FPGA chips for acceleration and emulation, optimizing the partitioning and routing of signals for simulation performance and creating glue logic and other logic transformations to enable emulation of the design. Responsible for interfacing with vendors and evaluating vendor software and hardware and new hardware architectures for the FPGA-based accelerator.

Used C and C++ for development. Verilog for simulation.

Gatefield Corporation (Actel Corporation) Fremont, CA USA 04/1998- 04/2000

Software Engineer

Developed software for Actel’s ProAsic flash-based FPGAs. Specified, designed and developed place, route, static timing analysis, hierarchical design methodology for hard IPs. GUI & front-end processing. Interfacing with software vendors for synthesis & test.

Used C++ for development.

Cadence Spectrum Services, San Jose CA USA 10/1996- 04/1998

Consulting Application Engineer

I worked as the bridge between customers and R&D groups on various projects, mainly for customers in Japan (Mitsubishi, Sony) and USA. Developed custom optimizations in Virtuoso layout synthesis to create ultra-compact standard cell layouts comparable in size to hand crafted layouts, using C and SKILL. Developed a tool to achieve timing closure after placement. Specified and worked on portions of the 7-day CSIC flow for Motorola Austin.

Used C and SKILL for development.

Cadence Design Systems Inc., Noida, India 06/1994 – 10/1996

Member of Technical Staff

Developed the place & route engine for the schematic generation software to import Verilog and VHDL into Cadence’s Composer & Concept databases. Using C on Solaris platform. Due to my exceptional performance and dedication, I was the only employee selected to be transferred to Cadence USA.

ENTREPRENUERSHIP EXPERIENCE 2003 - 2009

CEO/CTO

Started a web-based development company and developed several websites, such as mygiftwishes, india-list, etc. Developed and sold a Lead Management system software for few years, and also developed few custom PHP, MySQL, CSS, HTML & JavaScript based web-based client projects for many small businesses.

EDUCATION

PhD Computer Engineering 2007-2015

University of California, Santa Cruz (USA)

Conducted research in the areas of deterministic multi-threading, computer architecture and parallel processing. Took courses in chip design, DFT, graph theory, algorithm analysis, computer architecture, data mining, machine learning, artificial intelligence, technology management, etc.

PhD Projects included:

An LLVM compiler pass to perform static race detection in multi-threaded programs and make them deterministic.

A 3D IC thermal simulator using Nvidia’s CUDA processor.

Design verification, P&R, power and thermal analysis of the group’s out of order processor.

Used LLVM, C++, Nvidia CUDA for thermal simulation. Used Android SDK mobile development for a class project.

Bachelor of Technology (Hons) in Computer Science & Engineering 1990 - 1994

IIT Kharagpur (India)

Performed research on complexity of channel routing for VLSI design and published 2 papers.

Developed an expert system for medical diagnosis using fuzzy logic.

Used C, Fortran & some LISP for programming.

COMPETENCIES

Core

Extensive experience in developing software from customer input

Leading and guiding talented teammates and gravitating them towards successful projects.

Experienced in project management

Technical

Design Verification of semiconductor chips, Fault Simulation, Clock and reset domains (CDC/RDC), LINT, Low Power design & verification, Power optimization & analysis, Formal Verification, FPGAs, Emulation, Power rail & voltage drop analysis, P&R, Static timing analysis, Data Mining and Machine Learning

C, C++, Python Perl. TCL/TK, PHP, MySQL, LLVM compiler, multi-threading.

Verilog, System Verilog, UVM

Software methodologies and development processes.

Defining product and algorithmic specifications to drive projects to flawless execution, to excite customers.

PUBLICATIONS

Will be provided on demand.

Contact this candidate