Electronic Engineering Circuit Design
Resume:
Profile
With published work in IEEE Xplore and SpringerLink, I bring expertise in circuit design
and technology solutions as an electronic engineering professional. My B.Tech training at UPPCL equipped me with practical skills in infrastructure development, and communication systems. I've executed projects in home automation and circuit design, showcasing my knack for innovative solutions. My M.Tech thesis centred on optimizing Low Voltage and Low Power Operational Trans-conductance Amplifier, highlighting my analytical prowess and dedication to technological advancement. Publication
SpringerLink-A Comparative Performance Analysis of Different Methodology Operational Trans-Conductance Amplifier Using Cadence IEEE Xplore-Design and Implementation of Low Power Flipped Voltage Follower Differential Pair-based Summing Stage OTA.
Internship
Intern, Doordarshan, Varanasi (July, 2016 - June, 2016)
• Received hands-on training in broadcasting infrastructure, including communication processes and program editing.
• Learned about studio programming using various equipment in the broadcasting chain, covering satellite transmission (Uplink and Downlink) procedures.
Training, Uttar Pradesh Power Corporation Limited(July, 2019 - June, 2019)
• Conducted meter reading and temperature data analysis.
• Gained insights into the payment and refund processing cycle.
• Enhanced PGW Cron to improve PGW success rate.
• Upgraded COD system to client-based COD system, implementing specific client information and multilingual checkout.
Education
Degree Collage/ School
Branch/
Board
Year
CGPA/
Percentage
M.Tech
Institute of
Engineering And
Technology, (IET),
Lucknow
Micro
Electronics
2020 - 2022 CGPA: 8.56
B.Tech
Institute of
Engineering And
Rural Technology
(IERT), Prayagraj
Electronics
Engineering
2017 - 2020 CGPA: 7.93
Diploma
Government Girls
Polytechnic,
Varanasi
Electronics
Engineering
2014 - 2017
Percentage:
77.7%
Intermediate
M.P.B.I.C
Narayanpur Kaniyar,
Varanasi
UP Board 2014
Percentage:
80%
High School
S.B.B.P H.S.S Patel
Nagar, Varanasi
UP Board 2012
Percentage:
81.16%
Jyotsana
Personal Details
Lucknow
*************@*****.***
Domain
Analog and Physical Design
Publications & Social
Links
Publication (SpringerLink)
Publication (IEEE)
Skills
• Microsoft Office
• Cadence Virtuoso
• LT Spice
• Sparten-3
• C Programming
• MATLAB
• VHDL
• Xilinx, ISE 14.7
• Latex
Languages
• English
• Hindi
Hobbies
• Rangoli Making
• Cooking Indian
Food
Contact this candidate