Development Engineer Product and Test

Hanri Bouzari

*** *.*** ****** *****@*******.***

Laramie, Wyoming 82051 469-***-****

PROFESSIONAL SUMMARY

Senior Principal Test and Product Engineer with over 27 years of experience developing and integrating deep sub-micron SOC wafer probe and final production test programs, characterization, yield enhancement, and test time reduction. I am skilled in qualifying products through collaboration with the Design, Product, DFT, Technology, QA, and yield enhancement engineering teams into high-volume global semiconductor manufacturing sites.

TECHNICAL SKILLS

Credence Sapphire-ATE & TCU

Teradyne IGXL Ultra Flex, J750

Advantest 93K-ATE

Keithley, SMUs, Rack & Stacks

CMOS Process technologies

Statistical Analysis, DOE, ANOVA

JMP, DataPower, Galaxy, Minitab

Memory Process and IC fabrication

SPC, GR&R

C/C++, VB, Perl, Python

Lean Six Sigma Green Belt

Oscilloscope, Spectrum Analyzer

RELEVANT EMPLOYMENT HISTORY

Northrop Grumman Corp., Advanced Technology Lab – ATL Linthicum Heights, Maryland

Senior Principal Semiconductor Test Engineer 2/2018-5/30/2024

Responsible for wafer and package level semiconductor test activities. This includes both new product test development and production test support of digital, analog, mix signal devices.

Familiar with various tester platforms: Teradyne J750, Keithley, Advantest 93K- Experience with rack and stack type of test systems.

Typical tasks include identifying and evaluating test hardware, designing and debugging probe cards and package test fixtures. Verifying equipment operation and performance, troubleshooting issues, developing test code, documenting test plans and procedures, evaluating test data, managing, training, and certifying technicians and operators, and performing continuous test improvements.

Interfaced with multi discipline teams such as test, design, product, process, and quality/reliability engineers, and program managers to resolve issues, optimize test accuracy and capability, improved yields and tester throughput, and meet customer needs.

Collaborated with design, product engineers and program managers on failure analyses.

Identified and evaluated test hardware including modifying and debugging probe cards and package test fixtures.

Optimized test accuracy and capability, improved yields and testers throughput to meet customer needs.

Up keeping lab equipment by having equipment calibrated and performing preventing maintenance.

Participated in design, test-plan reviews, and test scenario requirements and communicated across teams effectively.

Collaborated with the site Quality Manager and engineers on all quality systems related aspects to ensure on time delivery of quality products.

Conducted Experiment-DOE using ATEs and operated oscilloscopes, source meters and analyzed scientific test data formats using Statistical Software packages such as JMP, Minitab, Excel.

Conducted troubleshoot and participated in the root cause of low yield the design of training materials to perform developed test code improvements.

Managed corrective and preventive action processes and maintain ATEs throughputs.

Repaired and replaced tester fixtures components using micro-soldering technique.

Calibrated optical apparatuses of EG-Electro Glass Probers & Exatron pick & place handler for higher throughput performance.

Communicates with vendors regularly to address any concerns and follow-up with the requirements of new parts and repairs.

Intel Corp. Santa Clara, California

System Validation Engineer- Contract 4/2017-1/2018

Implementing CPU Sub-System Characterization using the modified MVB evaluation board.

Conducting PCIe enumeration characterization using Analog Voltage rails of PCIe controller and PHY.

Working closely with PCIe PHY team to debug and improve Gen3 enumeration test.

Modified MVB-Module Validation Board with new sets of ECOs - Engineering Change Order.

Screening new device revs for 375 / 750MHz DDR, CPU, UART, DSP & PCIe using DS-5 ARM stream and Lauterbach JTAG.

Qualcomm Inc. San Diego, California

GPU Hardware – Post Silicon Validation Engineer – Contract 3/2015– 9/2016

Worked closely with the Power Management team to debug and characterize new current sensing of embedded PMIC.

Evaluated RMA units - GPU hangs at customer development boards. Created binary dump and kernel log files in

the android environment in MTP- Modem Test Platform debug board.

Executed and analyzed nightly or weekly regression runs to validate GPU blocks.

RELEVANT EMPLOYMENT HISTORY

Intel Corp. Austin, Texas

System Validation Engineer- Contract 6/2013- 2/2014

Expert in High-Speed I/O - MIPI DSI Protocol and debug, including knowledge of relevant debug tools (MIPI protocol, scopes, logic analyzers, Chip Scope, D-CAT-DSI (Capture and Analysis Tool).

Executed MIPI DSI Protocol Conformance and D-PHY Compliance testing across different Process Levels for Intel's upcoming Smartphone products.

Worked closely with other engineers to automate DSI tests on bench environment and analyzing the data.

Enabled MIPI DSI Protocol Conformance Test infrastructure by analyzing and help to debug various versions of D-CAT (DSI Capture and Analysis Tool).

Advanced Micro Devices – AMD Austin, Texas

Product Development Engineer, 1/2011 – 8/2012

ATaC (Advanced Test and Characterization) Functional Group – Contract

Developed test programs to bring up functional CPU core patterns for post-silicon validation of next-generation Multi-core CPUs/GPUs microprocessor package device on Credence – Sapphire ATE.

Implemented Functional Regression techniques to validate post-silicon test patterns for worse case limiters.

Performed and analyzed available CPU and GPU patterns limiters and found worse case speed paths in silicon debug using ATE to generate scan dump (RTL codes) files and used LICAT -AMD's laser tool in Failure Analysis improve process performance margin considerably.

Developed Circuit Sensitivity- mini characterization ATE program flow in functional testing to eliminate engineering involvement.

Panavision Imaging Homer, New York

Test Engineer, CMOS Imaging Sensor -Contract 9/2010- 1/2011

Developed final and wafer level test programs for CMOS Imaging Sensor –DLIS 2K on Teradyne – IP750

Published Test Program Overview and Preliminary test strategies to provide low-cost and effective solutions for high volume manufacturing for PE Department.

Developed and debugging functional test patterns for yield enhancement activities and collaborate closely with the design team for new pattern generation in a final test program.

Designed probe needle card and Probe Interface Board for TSK Prober.

NXP Semiconductors Austin, Texas

Test Engineer, Networking and Multimedia Group 5/2004 – 12/2009

Integrated and sustained final test program to market POWERQUICC- PQ38K Network Processor device on ATE - Teradyne UltraFlex tester.

Integrated pre-qualification test program on ATE from a team of 5 engineers and releasing test programs to the Test and Product Engineer team in offshore foundry site.

Developed and summarized characterization test suite Local Bus AC specs.

Implemented new sets of scan, jtag, and fused patterns for PQ38K Chartered test program.

Analyzed characterization data for FMAX, VDDMIN search with JMP.

Identified root cause of a process shift in pre-qualification HTOL reliability stress test failure by implementing various characterization techniques and shmoo plots.

Test / Product Engineer, Cellular Products Group

Developed and maintained wafer level and final test programs to market LTE2 mixed-signal wireless/baseband processor on Advantest/Verigy 93K.

Conducted weekly conference calls to TSMC & UMC PE/TE team for executing test programs transfer and ramp-up.

Improved scan yield for ATMC and UMC wafer probe by 5%, working with Advantest's Application Engineer and DFT team to develop additional engineering probe insertion.

Conducted process window split sample characterization and completed a statistical analysis of marginal data with Minitab.

RELEVANT EMPLOYMENT HISTORY

Maxim Integrated Products Dallas, Texas

Test Product Engineer II 11/2000-12/2002

Developed, modified, and debugged mixed-signal T1 Transceiver device silicon and final test programs on ATE – Teradyne Catalyst tester.

Characterized PLL of new products on bench test and correlated to ATE test program for production release.

Conducted yield enhancement, test time, and cost reductions were achieving the initial objectives of projects.

Converted test programs from one test platform to a different test platform.

Transferred and correlated test programs to offshore foundry site.

Monitored production cumulative yield trends and improved yield flows.

IBM Microelectronics Corp Essex Junction, Vermont

Senior Associate Product Engineer 5/1996 –11/2000

Established engineering and scientific analysis on problems such as fail signature analysis; coordinated physical failure analysis, and correlating fail modes and defects to process sector, in collaboration with DRAM Development Alliance-(IBM/IFX/Toshiba).

Provided direction and assisted manufacturing in achieving program productivity by monitoring module yield learning, parametric test data analysis, and yield support with SAS.

Monitored 256Mbit SDRAM cumulative module yield resulting and improved fab baseline defects and yield performance.

Investigated relevant trends in DC parametric versus in-line measurement trends.

Conducted fail corner signature analysis and correlated to In-Line measurements for low yield memory products.

Provided bit fail map analysis for the physical failure analysis team.

Associate Product Engineer

Analyzed data for Process Window tests on new 16Mbit SDRAM designs with statistics software.

Tested, debugged, and modified memory products were utilizing the Teradyne J997 Memory Tester.

Provided the necessary data analysis for the quality and reliability team's 16Mbit SDRAM and stacked memory functional testing.

Compared to other vendor SDRAM specifications, ensuring IBM memory products exceeded current market specifications.

EDUCATION & CERTIFICATION

Arizona State University Tempe, Arizona

Master of Science in Electrical Engineering Technology August 1995

Arizona State University Graduate College – Magna Cum Laude, Engineering Honor Society -Tau Beta Pi

Shahid Beheshti University Tehran, Iran

Bachelor of Science in Applied Statistics August 1986

Purdue University West Lafayette, Indiana

Lean Six Sigma Green Belt Certification July 2011

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